Confused by Prop-2 Interrupts

JonTitus

I understand how interrupts work with an ISR and how they get back to the interrupted software. The P2 documentation explains a cog may select interrupt event sources and it lists among them:

1. CT-Passed-CT1
a. CT is a free-running 32-bit counter. Does it run at the system-clock frequency, or can I set the increment rate? If so, how?
b. What the heck is CT1, a register? The assembly-language op-code spreadsheet notes: "ADDCT1... Set CT1 event to trigger on CT = D + S. Adds S into D." So, do I somehow (how?) get the CT value, add a value to it and wait until the CT > CT1? When might I need to interrupt on this type of event?

2. SE1 event occurred, established by SETSE1
SETSE1... "Set SE1 event configuration to D[8:0]." D[8:0] is a 9-bit value. Where do I find what these nine bits represent in terms of events? I find an example in the documentation, "SETSE1 #%001<<6 + adcpin" but no clue as to what it sets. Seems like it does something related to "adcpin" but I don't know what. Can someone point me to the D[8:0] information?

A couple of examples of interrupt use might help others. Thank you. Happy July 4th. --Jon

Ariba

It's all in the RevB silicon description PDF:

1a: it always runs with the system clock
1b: CT1..CT3 are 3 registers that can be compared to the CT counter value. You set it with ADDCTx. See the 'EVENT' chapter beginning at page 29.
Example on page 33.

2. Also in the EVENT chapter at page 31: 'POLLSE1/WAITSE1 event flag'

Andy

evanh

The function of SETSE1 is to configure that specific SE1 event hardware. There is 16 separate hardware event sources in each cog. So a total of 8x16=128 hardware event sources in a prop2. Each can be independently armed.

SETSE1 #%001<<6 + adcpin

What that is doing after the # is building a 9-bit constant at assembly time. It expects the value of adcpin to fit within six bits, ie: less than 64. The %001 then fills the three upper bits [8:6].

The %001 is 1 of 12 triggering modes that an SE1 event can be armed for. They are listed under the POLLSEx description in the "Events" section of the main doc, which is just before the "Interrupts" section.

JonTitus

Thanks, folks. I'm starting to catch on. Happy July 4th. --Jon

evanh

Notably, it's a little unusual to have so many special instructions for hardware configuration. Most other architectures will have memory or I/O mapped register space for this type of job. It's one of the reasons I portray the propellers as more of a load-and-store architecture.