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Prop-2 %10000 "Time A-Input States" How does IN get reset? — Parallax Forums

Prop-2 %10000 "Time A-Input States" How does IN get reset?

I drew the attached diagram to show what I think happens in the %10000 Time A-Input States mode. If software doesn't read the newest data with an RDPIN or RQPIN instruction, what resets the raised IN flag? And when would it get reset? It would seem to remain raised if software doesn't capture the data. Cheers. --Jon
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Comments

  • A RDPIN or AKPIN will clear the IN state of a smart pin, RQPIN does not.
    From the docs.
     RDPIN   D,S/# {WC}      - Get smart pin S/# result Z into D, flag into C, ack pin
     RQPIN   D,S/# {WC}      - Get smart pin S/# result Z into D, flag into C, don't ack
    AKPIN   S/#             - Acknowledge pin S/#  
    
  • Understand about AKPIN and RDPIN. Thanks. But what happens if my software goes off to do something else and misses the IN raised flag at the point between periods R and S. Does the IN flag stay set or does something automatically reset it? If it stays set, software might detect it in the middle of the "S" counting period.
  • YanomaniYanomani Posts: 1,524
    edited 2020-06-18 05:22
    It'll stay set, up to the moment a RDPIN or AKPIN instruction is executed, unless, of course, you reset the smart pin, by reversing its DIR.
  • jmgjmg Posts: 15,173
    edited 2020-06-18 05:36
    JonTitus wrote: »
    Understand about AKPIN and RDPIN. Thanks. But what happens if my software goes off to do something else and misses the IN raised flag at the point between periods R and S. Does the IN flag stay set or does something automatically reset it? If it stays set, software might detect it in the middle of the "S" counting period.

    Yes, but the captured totals are latched, so you have a full measurement cycle to respond.
    It's the same as any capture peripheral - if you are too slow in reading it, you may miss a N captures, but eventually read N+1 capture will be of a whole measurement cycle.

    If that possible missing was a problem, you could configure another pin cell to count measurement cycles, and read that too. If that was ever >1, it shows you missed reading one.
  • evanhevanh Posts: 15,916
    edited 2020-06-18 05:41
    JonTitus wrote: »
    ... If it stays set, software might detect it in the middle of the "S" counting period.
    Ya, it lets you know the counter has completed a measurement. It gives the software some slack to read the hardware measurement when it can.

    IN could be tied to an interrupt if you want.

  • YanomaniYanomani Posts: 1,524
    edited 2020-06-18 05:57
    If both the low and high states are very regular in the aspect of their duration, you can even capture CT (the system counter), either in its 32-bits, or 64-bits version, just after each IN is flagged, and, eventually, even before capturing C and the value of Z, so you can "time-tick" your captures, related to the evolution of CT.

    Then save the actual time-tick, and subtract the older one, before replacing the older with the new one, to be ready for subtraction, at the next capture of IN.

    This way, you can have a reasonable guess about if your routine did lost any measurements, or not.

    Both CT and the states counter evolve at the same rate (Sysclk), thus it'll be easy to spot any abnormal evolution at the value of Z. Also remember; the value of Z is limited to 80000000 counts, by design.
  • Thanks. To get results, does software wait for a carry = 1 and read the logic-1 period, then wait for a carry = 0 and read the logic-0 period, then wait for carry = 1 and read the next logic-1 period, and so on..?

    What happens if an input is constantly held as a logic-1 or a logic-0? Does the Z register indicate an overflow? --Jon
  • jmgjmg Posts: 15,173
    JonTitus wrote: »
    What happens if an input is constantly held as a logic-1 or a logic-0? Does the Z register indicate an overflow? --Jon

    The counter saturates, at $80000000, but has no overflow flag as such.
    The capture/transfer of that counter to the visible Z, occurs on the capture condition - here it is a state change. So no-state-change means no transfer.

    If reading of captures is too slow, the latest capture overwrites the un-read one, but has no error flag showing over-run.

    For teaching ports, it may be useful to have a simple dumper that stimulates pins at ~ 1 second rates (maybe pins 56,57.. on the LEDs on EVAL ?), and reports Smart Pin flags and pin states at maybe 100ms rates.

    That would let users see how each mode totals/captures/overflows etc

  • evanhevanh Posts: 15,916
    edited 2020-06-19 07:12
    JonTitus wrote: »
    To get results, does software wait for a carry = 1 and read the logic-1 period, then wait for a carry = 0 and read the logic-0 period, then wait for carry = 1 and read the next logic-1 period, and so on..?
    How it works is the smartpin, once DIR goes high, is actively making new measurements all the time. Z is updated with each completed measurement and IN is raised and the subsequent measurement is immediately underway. This subsequent measurement will be placed in Z as soon as it is done. Rinse and repeat ad infinitum.

    If the software doesn't read the measurement from Z in a timely manner then it will be lost when overwritten by the subsequent measurement. IN also stays high for these cases, ie: IN lowers when the measurement is read with RDPIN.

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