ECC memory

Rayman

Was just thinking about how my PC uptime increased rather dramatically when I switched to ECC memory.
I can go for months without rebooting now...

At the same time, my P1 based systems seem immune to bit flips on similar timescales...

I'm curious as to how this can be. I think P2 and P1 RAM is not ECC in any kind of way...

Anyway, maybe this is another idea for P3, ECC RAM. Or, maybe it's not an issue?
I don't think I've ever observed an error related to a bad bit in RAM....

Rayman

I was just reading this wiki page; https://en.wikipedia.org/wiki/Soft_error#Soft_error_mitigation

I think it may the combination of low memory count and high memory size (physical volume) that makes it so you don't see soft errors in microcontrollers...

Rayman

Actually, I was just reading that redundancy is a good what o mitigate any of this:
https://www.st.com/content/ccc/resource/technical/document/application_note/15/54/c4/5d/90/ed/4f/ce/DM00220769.pdf/files/DM00220769.pdf/jcr:content/translations/en.DM00220769.pdf

If it really matters, I guess make a twin copy of every variable and make sure they are identical before doing anything...

Still, I think ECC would ease minds...

cgracey

6T SRAM cells have positive feedback for holding state. Much smaller DRAM is 1T, only, needs to be refreshed, and is more easily upset.

evanh

I've had an external battery backed 32 kB SRAM flip a single bit on me after several years. It was in a servo controller that stored the source code on board and tokenised it on every power up. So the controller started spitting out a single syntax error to the comport on every power up. Edited the source, one character had changed, and away it went again.

Rayman

cgracey wrote: »

6T SRAM cells have positive feedback for holding state. Much smaller DRAM is 1T, only, needs to be refreshed, and is more easily upset.

Ok, that seems right. Thanks.

BTW: What does 6T mean? Is this the area of the cell?

rogloh

6 transistor

Electrodude

Rayman wrote: »

What does 6T mean?

Number of transistors. Two weak inverters (two transistors each) in a loop, plus two more transistors to access the state (read or forced override) makes six transistors.

Schematic here