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8-bit-level-comparator input mode? — Parallax Forums

8-bit-level-comparator input mode?

ManAtWorkManAtWork Posts: 2,176
in Propeller 2
In the P2 data sheet in chapter "OVERVIEW" I found "Each smart I/O pin has the following functions: ... - Logic, Schmitt, pin-to-pin-comparator, and 8-bit-level-comparator input modes". But I haven't found a hint how to setup this mode in the smart pin mode description.

I try to find out what is the simplest way to implement an overcurrent shutdown in a brushless motor driver. I have 3 current sensors which output an analogue voltage centered to 1.65V. When one of the sensors saturates, ie. goes below 0.3V or above 3V, I have to shut off the PWM power stages as fast as possible (within ~2µs). The sensor signals go to ADC inputs of the P2. But the ADCs are too slow because I configure them for maximum resolution. Also to cancel out noise and subsampling/alias effects with PWM ripple currents ideally the sigma/delta integration period should match the PWM period.

I have lots of pins left so if the analogue comperator feature works I could connect each signal to two additional pins implementing a window comperator with the DACs of that pins held at constant 0.3 and 3.0V. If not I have to add external comperator ICs.

Comments

  • evanhevanh Posts: 15,916
    I've named it COMP_DAC mode. Basic config info here - https://forums.parallax.com/discussion/comment/1452036/#Comment_1452036

  • ManAtWorkManAtWork Posts: 2,176
    Ah, thanks. So if DIR is 0 the output driver (feedback) is disabled and the comperator input is high impedance?

    Then I can use IN to trigger an interrupt so that I don't have to waste a cog for overcurrent monitoring, I assume.

    Maybe it's a good idea to have external hardware comperators, at least for the prototype. So shutdown is always guaranteed even if the software doesn't work. The cost of the comperators is neglible, but I fear I could run out of PCB space.
  • evanhevanh Posts: 15,916
    Yes to all. Interrupt trigger would be excellent use.

  • ManAtWorkManAtWork Posts: 2,176
    Is there something else to pay special attention in the layout?

    I've seen in the schematic that the P2 eval board uses a lot of seperate LDO regulators. Would this provide lower noise to the ADC and DAC pins if I reserve one of the 4 chip edges for analogue signals and spend it an extra low noise LDO?
  • evanhevanh Posts: 15,916
    edited 2019-12-16 12:18
    I wouldn't call myself an expert but my understanding is the mainonly benefit of separation into many LDOs is the separation of common mode I/O noise. ie: Other I/O inject noise onto the common supply rail. The noise will presumable look similar to crosstalk. I don't think there is any other benefit.

    The physical arrangement of the I/O supply rails in the prop2 is one per VIO pin, which each supplies just four I/O pins. So you could have up to 16 LDOs to gain maximum benefit.

  • evanhevanh Posts: 15,916
    edited 2019-12-16 13:00
    The prop2 doesn't take kindly to a voltage spike on its VIO pins. Make sure strong ceramic capacitors are used for all VIO supply pins. Same for VDD, but that's a given when clocking this fast.

    EDIT2: What has happened is a few of us got a fried I/O or two when shifting VIO jumpers on the revA Eval Boards with the power still on. A possible explanation is on jumper contact the neighbouring ceramics overwhelmed the immediate ceramics, triggered the latch-up, then the large storage caps of the switchmode delivered the destructive current. The revA board has two VIO sources of supply with a ring of jumpers to choose with.

    EDIT: V2831 (VIO pin) is special. It supplies the power for the crystal oscillator, the PLL oscillator, the two RC oscillators and the clock source select logic. Nothing runs without that supply up.

    V6063 may also hold the chip in reset (untested) if not powered.

  • ManAtWorkManAtWork Posts: 2,176
    16 LDO would be too expensive, anyway. At the P1 there was a dependency between current draw (computing/CPU load) and ADC drift. This should be de-coupled well at the P2 because VIO and VDD (core) use seperate power domains.

    I think I'll use a ferrite bead and extra C for the PLL/Osc and an extra LDO for the analogue subcircuit in the prototype. Then I can short this to normal VIO to check if there is a remarkable difference.
  • evanhevanh Posts: 15,916
    edited 2019-12-16 13:18
    Yeah, no need to have every option when it's a specialised layout. EDIT: Re-reading what I wrote, "maximum benefit" wasn't best choice of words. "maximum flexibility" would have been better.
  • jmgjmg Posts: 15,173
    ManAtWork wrote: »
    I've seen in the schematic that the P2 eval board uses a lot of seperate LDO regulators. Would this provide lower noise to the ADC and DAC pins if I reserve one of the 4 chip edges for analogue signals and spend it an extra low noise LDO?
    That was done for flexibility, you could go as low as just 2 LDOs.
    As mentioned above, one pin also powers VCO/PLL, so that should have special attention.

    A low noise LDO helps ADC and DAC operation. I selected NCP187AMT330TAG, as it has high peak current, and has Power Good pin. (P2 has no BOD)
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