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Order P2X8C4M64P now for April delivery (up to 990 units per customer!) — Parallax Forums

Order P2X8C4M64P now for April delivery (up to 990 units per customer!)

Ken GraceyKen Gracey Posts: 7,325
edited 2019-12-11 05:50 in Propeller 2
Hello Community,

Many customers have expressed concern about waiting until September 2020 to obtain P2X8C4M64P silicon chips from Parallax. We have a way to help production-minded customers and mitigate the impact of waiting.

Parallax has the opportunity to purchase up to 10,000 fully packaged engineering sample chips in a single order for April 2020 delivery. This is considered a "risk" purchase by Parallax. These chips will be marked P2X8C4M64PES as with previous engineering samples, with a new lot code, and include the A/D improvement (Rev C).

If you are interested in booking your order for the expected April in-stock date, these are the terms:
(a) Parallax will take responsibility that these parts meet the published specifications for the P2. Your purchase order is conditionally accepted until we validate the parts. If we introduced an error in the design you are not responsible for taking delivery.

(b) Our receipt of your purchase order will be by email to kgracey@parallax.com no later than December 17, 2019 (but preferred by this Friday, December 13, 2019). I will review and confirm the PO by reply to you. Payment will be by credit card or by check cleared prior to shipment, arranged around March.

(c) Your order is in tray unit increments (90 chips). Stock code to order is P2X8C4M64P-ES-T. Additionally, the minimum order quantity is 1 (90 chips) and the maximum order quantity is 11 (990 chips).

(d) Pricing is according to this price schedule: P2X8C4M64P-ES-T: $1,080.00 ea. ($12 ea)

If you need fewer than 90 units, you will likely be able to buy them from our regular inventory, but possibly at a higher per-chip price. We will attempt to order enough to support customers and tool development efforts until the production chips arrive (currently projected as September 2020). I need to determine our order quantity as soon as possible this week. We will at least order 3,000 units, but the additional quantities depend on purchase orders we receive as a result of this notification. Placing a purchase order now guarantees delivery.

You may be interested in the tentative price schedule we will have in place after April, in order to see how your pricing of a preordered P2X8C4M64P-ES-T by tray compares to our future pricing. While it is not yet formalized, we are considering the following.

Stock Code 1-10 10+ 100+ 1000+
P2X8C4M64P $14.95 $13.46 $12.71 $11.96

I should remind you that the Spin2 compiler has not yet been released by Chip but he's working diligently to make a release.

Thank you,

Ken Gracey
kgracey@parallax.com
(916) 625-3010 (direct line)

Comments

  • TubularTubular Posts: 4,404
    edited 2019-12-11 05:49
    Ok, this is great. Waiting until April is so much better than October

    It was getting frustrating having tried the P2 at various tasks successfully, but not being able to order more than 4 chips each. It artificially constrains development

    This also means you should have some products doing P2 things in the field, which people can talk about at the October launch party

    In talking with SMDA people they like a couple of months to get everything lined up, so April fits well with that.

    I'd better send through a PO for some trays. Ordering on Friday 13th and hopeful for delivery on April 1st.
  • JRetSapDoogJRetSapDoog Posts: 953
    edited 2019-12-11 06:15
    Thanks, Ken. The P2 is real! At least it's sampling. Here's a walk down memory lane: Attached is Parallax's backcover ad in the Aug. 2006 issue of Circuit Cellar. I realize that the prices of electronics go down over time (and the functionality goes up), but just for comparison, the P1 cost $25 at launch, which is about $32 adjusted for inflation. So, for QTY 1, the price of the P2c is about half the price back then, and it has maybe 20X the power (as a combination of increased pins, ram, speed, pin functionality and instructions).
    946 x 1286 - 323K
  • Cluso99Cluso99 Posts: 17,937
    Fantastic news Ken :smiley:

    For that price I hope ON are giving you a good price!
  • Ken Gracey wrote: »
    Stock Code 1-10 10+ 100+ 1000+
    P2X8C4M64P $14.95 $13.46 $12.71 $11.96

    Thanks, Ken, good news!
    ... include the A/D improvement (Rev C).

    Just for the uninformed newcomer like me... "Rev C" means it has the wighted average filter thing, but the latest capacitive coupling problem hasn't been fixed, right? I can live with the "use one pin pair for each A/D input" workaround.
  • "the latest capacitive coupling problem"..

    That will be fixed in Rev C.
  • cgraceycgracey Posts: 13,610
    VonSzarvas wrote: »
    "the latest capacitive coupling problem"..

    That will be fixed in Rev C.

    Right. The adjacent pin won't interfere with the local pin's A/D conversion, anymore, in the coming Rev C. The GIO and VIO calibration modes are still subject to coupling the local pin's signal, however. Until I can redesign the ADC's selector circuit and get the switches in front of the resistor array, we'll just have to live with that. The much bigger problem is out of the way, anyway, with the adjacent pin disconnected from the resistor array.

    When I have time to redesign the ADC, aside from fixing the remaining GIO/VIO coupling issues, I will put a selectable pure-resistor feedback mode in there, so that it can resolve very high frequency signals at somewhat lower resolution and impedance, but without the bandwith-limited analog front end that forms a delicate current balance. It would be good to be able to quantize signals in the 10's of MHz, too, rather than in just the 1's of MHz. It's exciting now to get Spin2 coming together, but I would be quite happy if I could just think about these ADC issues for the next few months.
  • evanhevanh Posts: 11,600
    edited 2019-12-11 15:21
    The ADC hardware filters (in the smartpins and the streamers) went into revB. It might not have been easy to spot the coupling issue without them.

  • Those are great news, Ken! I think, after all, there will be no difference between RevC chips and production chips. The silicon is already proven, apart from the capacitive coupling issue that will be solved, anyway.

    Kind regards, Samuel Lourenço
  • cgracey wrote: »
    It's exciting now to get Spin2 coming together, but I would be quite happy if I could just think about these ADC issues for the next few months.
    Say what? At the expense of Spin2? You need to get your mind right. Just kidding! It really is nice to focus on one thing at a time. But life doesn't usually cooperate.
  • jmgjmg Posts: 14,811
    cgracey wrote: »
    ...
    When I have time to redesign the ADC, aside from fixing the remaining GIO/VIO coupling issues, I will put a selectable pure-resistor feedback mode in there, so that it can resolve very high frequency signals at somewhat lower resolution and impedance, but without the bandwith-limited analog front end that forms a delicate current balance. It would be good to be able to quantize signals in the 10's of MHz, too, rather than in just the 1's of MHz. It's exciting now to get Spin2 coming together, but I would be quite happy if I could just think about these ADC issues for the next few months.
    That gets into diminishing returns area.
    There will always be better external ADCs that can be used, and any MHz you reach, will always be short of some users needs.
    A better area to put effort into, may be faster pin interfaces and control.
    When I look at External ADC parts, the 3V ones are fading, and the newest ones are all 1.8V io, some even move to JESD204B (A serial lvds type link)
    ADI have lower power ADCs in 1.8V, and look to only offer LVCMOS DDR parallel option, in the 1v8 models.
    Likewise, in memories, fastest & lowest power ones are in 1.8V
    As time moves forward, that issue will only get worse.


  • cgraceycgracey Posts: 13,610
    edited 2019-12-11 20:49
    jmg wrote: »
    cgracey wrote: »
    ...
    When I have time to redesign the ADC, aside from fixing the remaining GIO/VIO coupling issues, I will put a selectable pure-resistor feedback mode in there, so that it can resolve very high frequency signals at somewhat lower resolution and impedance, but without the bandwith-limited analog front end that forms a delicate current balance. It would be good to be able to quantize signals in the 10's of MHz, too, rather than in just the 1's of MHz. It's exciting now to get Spin2 coming together, but I would be quite happy if I could just think about these ADC issues for the next few months.
    That gets into diminishing returns area.
    There will always be better external ADCs that can be used, and any MHz you reach, will always be short of some users needs.
    A better area to put effort into, may be faster pin interfaces and control.
    When I look at External ADC parts, the 3V ones are fading, and the newest ones are all 1.8V io, some even move to JESD204B (A serial lvds type link)
    ADI have lower power ADCs in 1.8V, and look to only offer LVCMOS DDR parallel option, in the 1v8 models.
    Likewise, in memories, fastest & lowest power ones are in 1.8V
    As time moves forward, that issue will only get worse.


    Do you think it's viable, yet, to make a pure 1.8V I/O Propeller chip?

    It would be great to go to 1.8V for speed and homogeneity, but you can't even light some LED's at that voltage. No more N-well latch up problems, anyway. It would be great, if practical. What about driving 1.0V at 75 ohms impedance? You even need 3V to trigger HSYNC and VSYNC on VGA monitors.
  • JRetSapDoogJRetSapDoog Posts: 953
    edited 2019-12-11 21:09
    A single supply (1.8V) would make PCB routing layout somewhat easier (EDIT: for the P2 chip near the ground pad, I mean). On the other hand, it sounds like level shifters would be required for any hsync/vsync signals. And don't you use 2V p2p right now for the color signals? Would something lower be sufficient? Yeah, perhaps I'm too focused on VGA video applications.
  • jmgjmg Posts: 14,811
    cgracey wrote: »
    Do you think it's viable, yet, to make a pure 1.8V I/O Propeller chip?

    It would be great to go to 1.8V for speed and homogeneity, but you can't even light some LED's at that voltage. No more N-well latch up problems, anyway. It would be great, if practical. What about driving 1.0V at 75 ohms impedance? You even need 3V to trigger HSYNC and VSYNC on VGA monitors.
    That would be an OnSemi question :) (maybe this needs split to a separate thread?)

    What may be possible, is to make some small group of pins 1v8 only, (12?) and focus those on speed, and add some IO delay tuning. DDR is an obvious target.
    Maybe OnSemi even have some 1.8V LVDS IP that could use those pins too.., giving a HDMI boost ?

    HyperRAM and HDMI are 'demo-operational' now, as those are tuned, you'll get more idea of what needs improving.

  • If you're going to speak of making some pins, but not all, run at 1.8V, wouldn't it be best to do it to a whole 32-pin block? Just 12 is an arbitrary number, and probably won't be enough in many cases.
  • jmgjmg Posts: 14,811
    If you're going to speak of making some pins, but not all, run at 1.8V, wouldn't it be best to do it to a whole 32-pin block? Just 12 is an arbitrary number, and probably won't be enough in many cases.

    I'm expecting some caveats come with the 1.8V support. Right now, the level translators are slow, and get slower when VIO = 1.8V.
    A fast 1.8V IO pin, may have to drop some 3v3? analog? features, to reach the speed.
  • cgraceycgracey Posts: 13,610
    jmg wrote: »
    If you're going to speak of making some pins, but not all, run at 1.8V, wouldn't it be best to do it to a whole 32-pin block? Just 12 is an arbitrary number, and probably won't be enough in many cases.

    I'm expecting some caveats come with the 1.8V support. Right now, the level translators are slow, and get slower when VIO = 1.8V.
    A fast 1.8V IO pin, may have to drop some 3v3? analog? features, to reach the speed.

    Everything at 1.8V would be much faster, including DAC and ADC.
  • but then interfacing to anything external becomes more of a hassle. :(
  • RaymanRayman Posts: 12,172
    It would be great if vioxxxx could be anything between 1.8 and 3.3 v without penalty. But, this is very low on my priority list ...
  • cgraceycgracey Posts: 13,610
    Rayman wrote: »
    It would be great if vioxxxx could be anything between 1.8 and 3.3 v without penalty. But, this is very low on my priority list ...

    The problem is that 3.3V transistors slow way down as you get to 1.8V and you can't drive the 1.8V transistors to 3.3V.
  • evanhevanh Posts: 11,600
    That'll be a gate vs channel properties thing I imagine.

  • evanhevanh Posts: 11,600
    Back to BJTs then!
  • evanh wrote: »
    Back to BJTs then!
    Bizen quantum tunneling transistors perhaps!?
  • evanhevanh Posts: 11,600
    Holly crap, lol, I thought you were making something up. Decided to google it to see if there was some lore I'd not heard of only to find Bizen is real and and very new.
    “It is a bipolar mechanism, not mono-polar like a mosfet,” said Summerland. “You don’t have direct contact to the base like a BJT, and it is not oxide-isolated like a mosfet. Instead there is a tunnelling junction to the base well with heavy doping and an abrupt junction. The result is Bizen – bipolar-zener – which retains the advantages of traditional bipolar processing yet removes the disadvantages by using Zener quantum tunnel mechanics.”

    https://www.electronicsweekly.com/news/design/tunnelling-transistor-offers-logic-power-easy-make-ic-2019-10/

  • kwinnkwinn Posts: 8,693
    evanh wrote: »
    Holly crap, lol, I thought you were making something up. Decided to google it to see if there was some lore I'd not heard of only to find Bizen is real and and very new.
    “It is a bipolar mechanism, not mono-polar like a mosfet,” said Summerland. “You don’t have direct contact to the base like a BJT, and it is not oxide-isolated like a mosfet. Instead there is a tunnelling junction to the base well with heavy doping and an abrupt junction. The result is Bizen – bipolar-zener – which retains the advantages of traditional bipolar processing yet removes the disadvantages by using Zener quantum tunnel mechanics.”

    https://www.electronicsweekly.com/news/design/tunnelling-transistor-offers-logic-power-easy-make-ic-2019-10/

    Interesting reading, and no bull either.
  • cgraceycgracey Posts: 13,610
    kwinn wrote: »
    evanh wrote: »
    Holly crap, lol, I thought you were making something up. Decided to google it to see if there was some lore I'd not heard of only to find Bizen is real and and very new.
    “It is a bipolar mechanism, not mono-polar like a mosfet,” said Summerland. “You don’t have direct contact to the base like a BJT, and it is not oxide-isolated like a mosfet. Instead there is a tunnelling junction to the base well with heavy doping and an abrupt junction. The result is Bizen – bipolar-zener – which retains the advantages of traditional bipolar processing yet removes the disadvantages by using Zener quantum tunnel mechanics.”

    https://www.electronicsweekly.com/news/design/tunnelling-transistor-offers-logic-power-easy-make-ic-2019-10/

    Interesting reading, and no bull either.

    They are currently at 1um, it seems. To do something like an ARM chip, they said they'd need a few metal layers for the requisite routing, but no planarization, as so few metal layers can just lap over each other. It looks, to me, like this is currently practical for power applications that need a bit of logic, as well.
  • Refreshing this link to see if there are more orders before I place a proto-duction (our name) order for risk parts.

    Thanks to the many who have replied; this helps us plan with more certainty.

    I will also be sending out an e-mail to our P2 mailing list. If you are not on this, you should be: https://www.parallax.com/company/follow-us add yourself to "P2 Community".

    Ken Gracey
    Parallax Inc.
  • cgracey wrote: »
    Rayman wrote: »
    It would be great if vioxxxx could be anything between 1.8 and 3.3 v without penalty. But, this is very low on my priority list ...

    The problem is that 3.3V transistors slow way down as you get to 1.8V and you can't drive the 1.8V transistors to 3.3V.

    How then eg Microchip makes PICs with VDD/IO from 2.3 to 5.5V (eg PIC16F / ram retention 1.7V) or 1.8 to 3.6V (eg PIC16LF / ram retention 1.5V)?
    How are other 3.3V parts 5V tollerant?
    Can't the future Prop(?3) use the same technologies in its output stage for IO?
  • evanhevanh Posts: 11,600
    It'll be a speed trade-off. The prop could probably do 5 Volt I/O too if limited to 32 MHz.

  • Today will be the last day to pre-order the P2 from April delivery. Please contact me if you are still interested kgracey@parallax.com.

    Keep in mind that we will have additional inventory for general sale (and our own use in tools, modules, etc.) but no guarantees about how this inventory will be allocated can be made.

    Thanks,

    Ken Gracey
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