What is the maximum VIO voltage ?

Bean

I assume it is 3.3V, but I didn't see it anywhere in the docs.
Was hoping for 5.0V, but I realize that is probably not possible.

Bean

cgracey

3.6 volts is probably an upper limit. Starting around 4.3 volts, you can actually cause latch up.

JRetSapDoog

Piggybacking on Bean's thread: Similarly, is the range (min..max) for Vdd (core) published anywhere? I checked the docs once and didn't find it but could have easily missed it. Or is there a standard percentage (+/- from Vdd) that applies here for the 1.8v core power? By the way, on the upper end of the range, I think I read not to exceed 2.2V on the P2 eval.

cgracey

I've run VDD up to 2.5V. There doesn't seem to be much benefit in doing so, as the core becomes out of bias relative to VIO and the pins quit communicating. Just keeping it normally at 1.8 seems best, with the I/O at 3.3V.

JRetSapDoog

Good to know, Chip. Thanks. Yeah, no need to go intentionally higher. I do wonder how much Vdd could sag, though. I've not worked with switched supplies before, but, for example, I wonder if the P2 would operate (reliably) if the switched output voltage dropped to 1.7V under a heavy load (the P2 "running on all eights" and overclocked). And how "low can one go," I wonder. Again, I wouldn't intentionally run it under voltage (or over voltage), but just wonder about the safe range for Vdd. Or maybe the brownout circuit comes into play on the low end.

Don't laugh, but I was toying with the idea of connecting a P2 chip up to one of those cheap multi-turn trim pot adjustable buck regulator modules someday. And I just wondered what would happen under different loads or if physical vibrations slightly altered the output voltage (I don't think I'd trust a one-turn pot module, and even a multi-turn pot might be risky and perhaps could be bumped). Anyway, just thinking out loud for the moment.

@Bean, I'm not hijacking your thread; I'm lojacking it.