Interesting P2 Rev B Thermal/Clock/PLL Behavior

JRoark

I’m putting this out there because you just never know who might find this useful.

Today was “play silly overclocking games day”, which finds my P2-ES Rev B in an impromptu enviro chamber suffering clock and PLL settings at temperatures that likely make Chip cringe a bit.

On one of the early runs I found that as I ramped-up the temperature slowly, when I reached 120F at a 360 mhz PLL the P2 would run fine, but if I tried to reboot/redownload my test code with this same clock setting/temp this would cause the chip to take a few wobbly steps and then fall-over and quit. But if you reboot with the first few instructions in the download setting the clock just 5 mhz lower... and then you *immediately* change up to 360 mhz, the chip gets up and runs just fine until the temperature rises another 10F or so. In other words the PLL will run at temperatures/freqs that it can not start at, but if you “kick it” with a slightly lower starting freq, you can get it running and “shift to a higher gear”.

This is clearly some fringe behavior, but I’ll put it out there on the odd chance someone finds it useful for some test scenario or something.

Peter Jakacki

JRoark wrote: »

I’m putting this out there because you just never know who might find this useful.

Today was “play silly overclocking games day”, which finds my P2-ES Rev B in an impromptu enviro chamber suffering clock and PLL settings at temperatures that likely make Chip cringe a bit.

On one of the early runs I found that as I ramped-up the temperature slowly, when I reached 120F at a 360 mhz PLL the P2 would run fine, but if I tried to reboot/redownload my test code with this same clock setting/temp this would cause the chip to take a few wobbly steps and then fall-over and quit. But if you reboot with the first few instructions in the download setting the clock just 5 mhz lower... and then you *immediately* change up to 360 mhz, the chip gets up and runs just fine until the temperature rises another 10F or so. In other words the PLL will run at temperatures/freqs that it can not start at, but if you “kick it” with a slightly lower starting freq, you can get it running and “shift to a higher gear”.

This is clearly some fringe behavior, but I’ll put it out there on the odd chance someone finds it useful for some test scenario or something.

I have noticed that in some of my earlier tests and used that workaround too, so thanks for the reminder
But we do know that we are operating well outside the design limits of course

JRoark

Yup! We’re a country mile out of spec here. From memory, wasnt the P2 spec’d at something like a 180 mhz clock?

Wuerfel_21

The spec is fairly conservative, it seems.
Most chips don't like being clocked at TWICE their max speed under any conditions.

evanh

JRoark wrote: »

... wasnt the P2 spec’d at something like a 180 mhz clock?

Yep, that was the target during synthesis but On Semi had to dial it back a little to 175 MHz in the end.