SVGA over HDMI at 38 Hz refresh
Rayman
Posts: 14,646
This one monitor of mine (Samsung s32d850t ) seems to accept crazy low refresh rates...
It's letting me do 800x600 with 250 MHz P2 clock, resulting in 38 Hz refresh rates.
The other monitors I have require vertical refresh to be very near 60 Hz.
It's letting me do 800x600 with 250 MHz P2 clock, resulting in 38 Hz refresh rates.
The other monitors I have require vertical refresh to be very near 60 Hz.
Comments
'*********************************** '* 720p24 HDMI - 16bpp 5:6:5 RGB * '*********************************** CON hdmi_base = 8 DAT org ' ' ' Setup ' hubset ##%1_010011_0100101000_1111_10_00 'configure PLL, 20MHz / 20 * 297 * 1 = 297MHz waitx ##20_000_000 / 200 'allow crystal and PLL 5ms to stabilize hubset ##%1_010011_0100101000_1111_10_11 'switch to PLL setxfrq ##$0CCCCCCC+1 'set transfer frequency to 1/10th clk, +1 for initial rollover setcmod #$100 'enable HDMI drvl #hdmi_base + 7<<6 'enable HDMI pins wrpin ##%10110_0011_0000_10_00000_0,#hdmi_base + 7<<6 '123-ohm DAC ' ' ' Field loop ' field mov hsync0,sync_000 'vsync off mov hsync1,sync_001 callpa #5+10,#blank 'top blanks mov x,##720-20 'set visible lines line rdfast #640*2/64,addr 'set rdfast to wrap on bitmap call #hsync 'do horizontal sync xcont m_rf,#1 'do visible line cmp x,#351 wz if_nz cmp x,#1 wz if_nz add addr,##640*2 if_z mov addr,base djnz x,#line 'another line? callpa #20+10,#blank 'bottom blanks mov hsync0,sync_222 'vsync on mov hsync1,sync_223 callpa #5,#blank 'vertical sync blanks jmp #field 'loop ' ' ' Subroutines ' blank call #hsync 'blank lines xcont m_vi,hsync0 _ret_ djnz pa,#blank hsync xcont m_bs,hsync0 'horizontal sync xzero m_sn,hsync1 _ret_ xcont m_bv,hsync0 ' ' ' Initialized data ' sync_000 long %1101010100_1101010100_1101010100_10 ' sync_001 long %1101010100_1101010100_0010101011_10 ' hsync sync_222 long %0101010100_0101010100_0101010100_10 'vsync sync_223 long %0101010100_0101010100_1010101011_10 'vsync + hsync m_bs long $7F910000+110 'before sync m_sn long $7F910000+40 'sync m_bv long $7F910000+220 'before visible m_vi long $7F910000+1280 'visible m_rf long $BF950000+1280 'visible rfword rgb16 (5:6:5) base long $1000 addr long $1000 ' ' ' Uninitialized data ' x res 1 hsync0 res 1 hsync1 res 1 ' ' ' Bitmap ' orgh $1000 - 70 'justify pixels at $1000 file "birds_16bpp.bmp" 'rayman's picture (640 x 350)This program runs at 297MHz and uses bit-DAC mode to drive the HDMI pins. The display is 1280 x 720. My image (actually, yours) is 700 lines long, so I added 10 extra top and bottom blank lines.
I see where you have the base pins set. How many I/o pins are required? Looks like only 3 in your code.
Is there a pin connector diagram anywhere to hook up an HDMI connector.
There may also be a way to reverse the output order (for connectors on reverse side of board etc)
There are 8 pins involved.
when you see this expression "#hdmi_base + 7<<6" it means affect pin[hdmi_base], plus the 7 pins above it, all together.
I just downloaded the spec sheet to see what it oficially says ... alas, it provides no data for sync ranges.
Trust but verify is applicable to data sheet claims. I learned that the hard way when trying to find replacement monitors for early medical imaging systems. That was a learning experience in magnetic deflection circuitry, scan linearity, video timing and signal levels, phosphor decay times, and other esoteric goodies.