Ran jumper from Test to ground and added 10k pullup resistor on RESn.
The only other issue I have at the moment is that my micro-USB connector did not import correctly from Diptrace.
The feedthrough slots became just holes that are too small...
But, I just got a replacement from SnapEDA, should be all better.
I did up reference schematics and pcb layout early last year as part of doing up a datasheet just so people wouldn't get caught. Guess this is a case of "RTM" The link is in bold in my sig but there are many documents there too.
Peter did all the work for you a year ago in black and white and pretty colors.
My Dropbox link shares all my P2 files totally openly, including all my notes, documentation, schematics, PCBs, photos, code etc etc. It's all there. However here is a png of my current schematic for reference. (ignore pin 2 connection, it goes to 1.8V)
Testing HDMI with Chip's example in documentation...
Bird image is not coming out of the transporter exactly right.
Hmm that's weird. I haven't seen anything like that in my experiments..
What pin mode signal levels are you using? I looked at some of Chip's code which I had a problem with initially and I thought the differential signal current seemed a bit low to get the drive required. I'm actually boosting up to a 3.3V swing which is most definitely breaking the TMDS electrical spec. The thing is that issue should cause dropouts or complete loss of sync, unless the TV you are using is buffering old data when the signal drops out. Seems more like a FIFO block wrap source address problem.
The problem with hand soldering this one is the ground pad...
If you made a couple big vias under the ground pad, you could probably solder it from the back side.
After hand soldering the top.
I like to use a lot of solder and then use solder wick to remove the excess...
You have to use FTDI's "FT Prog" utility to make the power enable and tx/rx led's work as intended...
These are on the C0 .. C3 pins.
Here is how I set them for this board (see image).
There are some other things I probably should change such as "Max Bus Power" probably should be 500 mA instead of 90 mA.
"Pull down IO Pins in USB Suspend" sounds like a good idea? Maybe not.
Was finally able to test out LSM9DS1 and RTC.
I think that was the last thing.
Everything works!
But, I did make a mistake with the I2C address pins on the LSM9DS1.
I should have grounded them, but instead left them floating.
Fortunately, they appear to have a pullup (or at least act that way).
Shoot. About to order some new boards, but found a DRC error on my new micro-usb connector.
Seems the side pads are shorting 5V pin to ground.
I got this footprint and symbol from Digikey via SnapEDA (part# 609-4618-1-ND)
Seems I need to manually make the pads less wide..
This is a really bizarre "feature" of Eagle...
Seems there is a "restring" parameter in the Design Rules that will make Eagle automatically change the pad sizes of library components when you import them...
Learn something new...
Anyway, had to make this change to pad design rules to fix this part.
Now, I have to check everything else to make sure this didn't break something else...
Shoot. About to order some new boards, but found a DRC error on my new micro-usb connector.
Seems the side pads are shorting 5V pin to ground.
I got this footprint and symbol from Digikey via SnapEDA (part# 609-4618-1-ND)
Seems I need to manually make the pads less wide..
That's too bad. Any chance it could be "unshorted" with a dremel or small triangular file so you can at least use it to verify the rest of the board?
Fortunately, I didn't order these boards yet, was just running a final DRC check...
This "restring" thing is horrible... The above % setting made the pads around my HDMI connector way too tiny... Increased back to 25% while leaving min at 4 mil and looks better now.
Ugh... I had to go into the library and manually change hdmi connector pad diameters from "auto" to something reasonable to fix it.
You definitely need to check all footprints before you use them. That’s why many of us oldies use old pcb software with our own proven footprints.
Even the so-called standards footprints can have problems. I recall when I was using my first 100 pin QFP and I went to the Australian Standards to find the recommended pad sizes etc. I found that they had based the pins on the wrong base (think it was based on metric but the pad pitch was actually imperial). Anyway, by the time you got to the 25th pin on the side, it was half a pad out. Rang our great standards department who said they copied the UK Standards. They had no intention of fixing the error!!! So much for paid standards publications. Fortunately I checked before using them.
Moral of the story... Check everything before you use it.
It was a Xilinx FPGA back in the early 90’s and I am fairly sure it was actually based on something like .20” or .25” unlike the current stock of ICs. The reason I am fairly sure is we are metric and so the pitch in the standards was shown in metric but the chip was actually imperial. Remember 25-30 years ago most chips were designed in the US and so imperial was still predominantly used.
Found the XC2064 PLCC68 package was imperial 0.050” imperial but haven’t been able to find the QFP100 spec.
Actually it was designed around 1985. Unfortunately cannot get to the full data sheet on my iPad. IIRC I used the XC2064 and I hand routed my design to get max throughput - the Xilinx software back then let you do this. I still have a printout of this in my filing cabinet
I used the FPGA to interface to the ICL System 25 Minicomputer processor bus backplane for a 16 port RS232 Serial Port card that I designed. One of my customers had 10 of my cards in one of his computers supporting around 120 remote terminals concurrently, located all over Australia via 9600 baud leased lines and Scitec Statistical Multiplexors.
Would have loved a P2 back then . Or even a P1 I used a pair of Z8681 with 8x Z8530 SCC’s and a Dual Port SRAM.
I looked at FPGAs in 1996 and remember reading about the Xilinx 6k series with its programming bus interface and fine grain approach for dynamic reconfiguration. It never matured any further though, and was already an EOL product even then. I do wonder if Xilinx ever plan to revisit the idea.
Actually the FPGA I used in 1990 was XC2018 - a PLCC84. Here is a pic, plus part of the hand-routed FPGA printout.
The FPGA device that had the standards dimension problem was in fact from my 1995 8-port 336K modem card for the PC. I couldn't easily locate the schematic and the brochure we made isn't clear enough to see the FPGA marking and I didn't keep a sample. It's a Xilinx 160-pin QFP. pic attached
Comments
Ran jumper from Test to ground and added 10k pullup resistor on RESn.
The only other issue I have at the moment is that my micro-USB connector did not import correctly from Diptrace.
The feedthrough slots became just holes that are too small...
But, I just got a replacement from SnapEDA, should be all better.
Kind regards, Samuel Lourenço
Maybe because I'm using Microchip SST26VF064 instead of Winbond W25Q128?
Seems P2 I/O is OK.
Peter did all the work for you a year ago in black and white and pretty colors.
https://www.dropbox.com/s/mlbr1kcet47aowo/P2 shortform.pdf?dl=0
Bird image is not coming out of the transporter exactly right.
Hmm that's weird. I haven't seen anything like that in my experiments..
What pin mode signal levels are you using? I looked at some of Chip's code which I had a problem with initially and I thought the differential signal current seemed a bit low to get the drive required. I'm actually boosting up to a 3.3V swing which is most definitely breaking the TMDS electrical spec. The thing is that issue should cause dropouts or complete loss of sync, unless the TV you are using is buffering old data when the signal drops out. Seems more like a FIFO block wrap source address problem.
Worked right on a simpler monitor...
Can you recommend someone who can solder the surface mount chip to a board. I will be embarking
on my own boards soon.
Thanks
They are probably expensive though...
If you made a couple big vias under the ground pad, you could probably solder it from the back side.
After hand soldering the top.
I like to use a lot of solder and then use solder wick to remove the excess...
You have to use FTDI's "FT Prog" utility to make the power enable and tx/rx led's work as intended...
These are on the C0 .. C3 pins.
Here is how I set them for this board (see image).
There are some other things I probably should change such as "Max Bus Power" probably should be 500 mA instead of 90 mA.
"Pull down IO Pins in USB Suspend" sounds like a good idea? Maybe not.
I think that was the last thing.
Everything works!
But, I did make a mistake with the I2C address pins on the LSM9DS1.
I should have grounded them, but instead left them floating.
Fortunately, they appear to have a pullup (or at least act that way).
Seems the side pads are shorting 5V pin to ground.
I got this footprint and symbol from Digikey via SnapEDA (part# 609-4618-1-ND)
Seems I need to manually make the pads less wide..
Seems there is a "restring" parameter in the Design Rules that will make Eagle automatically change the pad sizes of library components when you import them...
Learn something new...
Anyway, had to make this change to pad design rules to fix this part.
Now, I have to check everything else to make sure this didn't break something else...
That's too bad. Any chance it could be "unshorted" with a dremel or small triangular file so you can at least use it to verify the rest of the board?
This "restring" thing is horrible... The above % setting made the pads around my HDMI connector way too tiny... Increased back to 25% while leaving min at 4 mil and looks better now.
Ugh... I had to go into the library and manually change hdmi connector pad diameters from "auto" to something reasonable to fix it.
Will hopefully be able to share proven Eagle design files for P2 soon.
Doing two variants. Both lose the nunchuck and add an extra USB port.
One will have a VGA connector. The other will have a Newhaven EVE2 display connector (hoping to test out 4-bit SPI intereface).
Even the so-called standards footprints can have problems. I recall when I was using my first 100 pin QFP and I went to the Australian Standards to find the recommended pad sizes etc. I found that they had based the pins on the wrong base (think it was based on metric but the pad pitch was actually imperial). Anyway, by the time you got to the 25th pin on the side, it was half a pad out. Rang our great standards department who said they copied the UK Standards. They had no intention of fixing the error!!! So much for paid standards publications. Fortunately I checked before using them.
Moral of the story... Check everything before you use it.
Found the XC2064 PLCC68 package was imperial 0.050” imperial but haven’t been able to find the QFP100 spec.
Actually it was designed around 1985. Unfortunately cannot get to the full data sheet on my iPad. IIRC I used the XC2064 and I hand routed my design to get max throughput - the Xilinx software back then let you do this. I still have a printout of this in my filing cabinet
I used the FPGA to interface to the ICL System 25 Minicomputer processor bus backplane for a 16 port RS232 Serial Port card that I designed. One of my customers had 10 of my cards in one of his computers supporting around 120 remote terminals concurrently, located all over Australia via 9600 baud leased lines and Scitec Statistical Multiplexors.
Would have loved a P2 back then
EDIT: And PLCC's were usually socketed then too. So a surface mount CAD footprint could have been hard to come by.
The FPGA device that had the standards dimension problem was in fact from my 1995 8-port 336K modem card for the PC. I couldn't easily locate the schematic and the brochure we made isn't clear enough to see the FPGA marking and I didn't keep a sample. It's a Xilinx 160-pin QFP. pic attached
Certainly a trip down memory lane