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Notes and progress for the new 64004-ES Hyper Memory accessory — Parallax Forums

Notes and progress for the new 64004-ES Hyper Memory accessory

VonSzarvasVonSzarvas Posts: 3,450
edited 2019-09-23 10:27 in Propeller 2
Thread to document progress, for members that are experimenting with the new Hyper Memory.

Starting with a reset tip..

You will need to assert IO+15 high to enable the memory module.

IO+15 by default holds the memory chips in reset, so that when inserted they always power-up in a sane cleared state.

This function can be changed by adjusting R204 positions thus:
1. Reset held by 10K to VSS (default setting)
2. Reset controlled by external reset (ie. hook to RESn on the RevB Eval board) 
3. Remove R204 to have module always on.

Check the schematic and docs for full information.

Comments

  • TubularTubular Posts: 4,702
    Yes this is IO+15 reset high is good advice

    The other thing to note is the early schematic (that had 27 ohm resistors) had different pin use for P9-12 to the final version
  • ozpropdevozpropdev Posts: 2,792
    Board seems to be different to schematic 
    +8 hyperram CK
+10 Hyperram RWDS
+12 Hyperram CS
+9 Hyperflash CK
+11 Hyperflash RWDS
+13 Hyperflash CS
  • TubularTubular Posts: 4,702
    Yep, thats the default config.

    The Hyperram is "Hyper A", and the Hyperflash is "Hyper B", since each site could be loaded with either type of memory separately, if the corresponding chip select jumper is changed over. But the default of one of each is good

    By default IO+14 is the interrupt signal, and is connected to Hyper B (Flash) Int signal, I believe
  • ozpropdevozpropdev Posts: 2,792
    Here's a capture of a Hyperram read transaction.
    HR_read.jpg
    800 x 600 - 93K
  • VonSzarvasVonSzarvas Posts: 3,450
    Looks good!

    Have you been able to measure throughput speed yet?
  • whickerwhicker Posts: 749
    Here's the code I wrote for a HyperRAM test board.
    It requires FastSpin Version 3.9.33 to compile.
    I set up the pins from ozpropdev's screen capture for it being plugged into P32 and up.

    What it is, is a terminal style program for exercising the HyperRAM. It expects capital letters.

    You can press L to change the latency clock setting, from 3 to 6. For performance reasons of course you want 3.
    Choose (F)ixed or (V)ariable latency. Variable isn't supposed to work if it's a dual stack chip.
    The printout of "Transitions" is how many clock transitions it took for RWDS to respond.

    Press (A) to change the command address. Then after entering that you can press (W) to write a value, and (R) to read it back or (B) to burst read it back.
    Read or Burst Read is controlled by (N), number of words to read (1 to 128).

    I'm available for any questions.
    bas
    bas
    HyperDiag12.bas
    18K
    Diag12-1.png
    677 x 474 - 43K
    Diag12-2.png
    677 x 654 - 45K
  • VonSzarvasVonSzarvas Posts: 3,450
    edited 2019-09-24 09:36
    Thank you @whicker

    Are you on the RevA or RevB eval?

    Is anyone aware of code changes between the 1st and 2nd version P2 chips ? I mean... will the HyperRAM and HyperFlash code need adjusting between the chip versions; does your code includes instructions that might have changed ?

  • whickerwhicker Posts: 749
    I've got Rev A.
  • evanhevanh Posts: 15,916
    VonSzarvas wrote: »
    Is anyone aware of code changes between the 1st and 2nd version P2 chips ? I mean... will the HyperRAM and HyperFlash code need adjusting between the chip versions; does your code includes instructions that might have changed ?
    Off the top of my head: Streamer mode numbers are completely re-encoded, and some have extra functions. The PTRA/B changes could affect tables in hubRAM.

  • ozpropdevozpropdev Posts: 2,792
    Thanks @whicker
    Tested on Rev A & B Eval boards with latest Flexgui Ok.
  • evanhevanh Posts: 15,916
    VonSzarvas wrote: »
    Check the schematic and docs for full information.
    Where is the schematic and docs?

  • PublisonPublison Posts: 12,366
    edited 2019-10-24 08:52
    evanh wrote: »
    VonSzarvas wrote: »
    Check the schematic and docs for full information.
    Where is the schematic and docs?
    I found a PDF of the schematic (about half way down):
    https://forums.parallax.com/discussion/170229/memory-breakout-poll/p4
  • TubularTubular Posts: 4,702
    edited 2019-10-24 08:59
    That schematic wasn't the final setup. For the working driver OzPropDev made Hyper A uses P8, 10, 12 for its signalling and Hyper B uses P9, 11, 13. I think the resistor values changed a bit too.

    I don't know the full history but just advise anyone to proceed with caution until something truly definitive is put up (product page?)

  • VonSzarvasVonSzarvas Posts: 3,450
    The final schematic will be published by the time the product gets to the shop. (Maybe later next week)

    If anyone who's got engineering samples of the HyperRAM module needs a provisional schematic, please PM me.
  • VonSzarvasVonSzarvas Posts: 3,450
    @evanh Hot of the press, the production schematic file attached. Source files will be in the store soon.

    Shout if any other details would be handy!
    pdf
    pdf
    64004-ES-REVA-HyperRAM_FLASH-20190721-SCHEMATIC-OS.pdf
    140K
  • evanhevanh Posts: 15,916
    Thanks Von. I probably can't comment much since I don't actually have the accessory. My mistake for not squawking at the right time.

    There was something I was looking for but can't remember right now. May have just been the hyperRAM component part number so I could get details on coding up timings.
  • JRoarkJRoark Posts: 1,215
    @VonSzarvas Yay for HyperRAM/HyperFLASH!!!

    But I have a query: I'm looking at the P2-ES Eval HyperRAM/Flash Add-on" schematic and I'm trying to understand the seemingly conflicting markings for U100 and U101.

    There are three pins on U100 that are marked "RFU", but they connect to "HyperA_FLASH_CS#", "HyperA_FLASH_INT#", and "HyperA_FLASH_RST0#", respectively. This seems contradictory to me.

    These same three pins, on U101, instead of being marked "RFU", are marked "CS#", "INT#" and "RST0#". This chip also has a connection marked "DNU" that is connected to "HyperB_RAM_CS#". This also seems contradictory to me.

    I'm assuming that "RFU" means "Reserved for Future Use" and "DNU" is "Do Not Use", but these pins are clearly being used. I'm sorta confuzzified here...
  • VonSzarvasVonSzarvas Posts: 3,450
    Some pins are required for Flash, but not for RAM. (or have a different pin position in the case of #CS).

    It will all work as supplied, as Parallax will set the jumper resistors in the right places for a board with 1x HyperRAM and 1x HyperFlash installed.

    For customers that choose to swap the memory chips, they may need access to those other pins.

    Some possible combinations are:

    2x HyperRAM
    2x HyperFlash
    1x HyperRAM, 1x HyperFlash
    2x Dual HyperRAM/HyperFlash (or 1x Dual and 1x any single type you like)


    So if the installed Hyper device doesn't need the pin, it won't use them. But they are available for any device that needs them.
  • JRoarkJRoark Posts: 1,215
    VonSzarvas wrote: »
    Some pins are required for Flash, but not for RAM. (or have a different pin position in the case of #CS).

    It will all work as supplied, as Parallax will set the jumper resistors in the right places for a board with 1x HyperRAM and 1x HyperFlash installed.

    For customers that choose to swap the memory chips, they may need access to those other pins.

    Some possible combinations are:

    2x HyperRAM
    2x HyperFlash
    1x HyperRAM, 1x HyperFlash
    2x Dual HyperRAM/HyperFlash (or 1x Dual and 1x any single type you like)


    So if the installed Hyper device doesn't need the pin, it won't use them. But they are available for any device that needs them.

    Sweet! Thanks for the clarification.
  • PublisonPublison Posts: 12,366
    Now that there will be a new run of RevB P2ES board, will there be a new run of HypeRam boards, (64004-ES)? There are only 5 in stock.
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