I will do some more VGA experiments tonight. I will start up more cogs to create more noise and try higher frequencies.
Here's the tests and photos from when we were trying to exacerbate and measure (via photos) the pll wobbles.
We were driving single color (green) VGA at 2048 x 1536 into a Rogloh's Sony G20 monitor.
I think the dot clock was 210 MHz, using "Vesa RB1" blanking standard. I don't think the monitor supported the Vesa RB2 standard.
In addition, we needed to cycle things up and down using a halogen floodlight as a kind of gentle radiator. The wobbles were somewhere around 20 or 30 degrees above the free air natural temp of the prop (ie the additional heat was required to bring them on)
I don't think we had many cogs running, but I'm sure it wouldn't hurt.
When it comes to computers I feel that the IBM 360/370 system that I learned on is in Jurassic Park compared to this.
Thank you so much. To make me feel ancient.
I haven't applied heat, yet, but I can't get pixel shimmying, even at 380MHz with the worst PLL settings. This monitor lacks the resolution needed, to be fair about it. Next, I need to get HDMI component video working. That's 1080p at a 148.5MHz pixel rate using three analog signals (Y, Pb, Pr).
Wow.
Impressive, and impressively compact code - but needs more comments for users to follow what P2 is doing here.
With ASM examples, I like to include a comment appendix that shows
; Build command lines
; Code Size reports
; % CPU used for the example, here that would be COG cycles spare
I guess this first HDMI test example simply uses 3.3V logic levels for now. In time it will be good to see if the pin settings for differential voltages and impedances compatible with CML do fully work with it too. I think some of that was discussed in another thread (probably that long HDMI one). It's fabulous to see the internal TMDS encoding and streamer change is working, regardless of the analog side.
I guess this first HDMI test example simply uses 3.3V logic levels for now. In time it will be good to see if the pin settings for differential voltages and impedances compatible with CML do fully work with it too. I think some of that was discussed in another thread. It's fabulous to see the internal TMDS encoding and streamer change is working, regardless of the analog side.
I think you can get close to HDMI signal levels with a simple series resistor ?
Maybe the adapter board Chip is using, includes those ?
Chip,
When i was seeing jitter/shimmering I was dividing the input xtal/osc to give 0.5MHz and then multiplying that up. This was on VGA 1920x1080. As i am away, perhaps you can try this???
On the v1 chip, it didn't matter what the resolution was, it happened at all divide values, with stronger effect at higher values. Many people, including Chip, tested it out and got the same effect.
In my testing (which was posted in the appropriate thread) that using 0.5MHz as the base (12MHz / 24 on P2D2) showed shimmering/jitter. Chip suggested using a smaller divisor yielding 4MHz as the base and multiplying that up. This removed the shimmering/jitter.
So this needs retesting. Unfortunately I won’t be back in Oz until 25th Aug. While i have my P2D2 with me, i don’t have access to a VGA 1920x1080 monitor here.
I guess this first HDMI test example simply uses 3.3V logic levels for now. In time it will be good to see if the pin settings for differential voltages and impedances compatible with CML do fully work with it too. I think some of that was discussed in another thread (probably that long HDMI one). It's fabulous to see the internal TMDS encoding and streamer change is working, regardless of the analog side.
There's a pin mode that uses the dacs to drive the digital output pin, the advantage being both the absolute High level and Low level can be one of 16 values (0.0 through 3.3v) , so it should be possible to do something approaching CML
0 5 0
%101_VV_DDDDDDDD = DAC_MODE (%TT = 00 and %MMMMM = 00000), 8-bit flash
OUT enables PinA ADC (ADC config %011), sysclocked bitstream on IN
DIR enables PinA DAC output
%VV = PinA DAC config
00: 990 ohm, 3.3 volt range
01: 600 ohm, 2.0 volt range
10: 123.75 ohm, 3.3 volt range
11: 75 ohm, 2.0 volt range
%DDDDDDDD = DAC level
for %TT = %01 and %MMMMM = %00000, %101_VV_xxxxSSSS = COG_DAC mode
%SSSS = Cog/streamer select: sets DAC level (registered?)
for %00000 < %MMMMM < %00100 = SMART_DAC mode
DIR/IN are usual smartpin ctrl
%DDDDDDDD ignored, smartpin sets DAC level (registered?)
for %MMMMM >= %00100 or (%TT = %1x and %MMMMM = %00000) = BIT_DAC mode
OUT sets DAC level (clocked?, ADC disabled?, IN = ?)
0: 0 = GIO level
1: %DDDDDDDD
PS: It has changed in the v2 chip to two 4-bit levels. With the v1 chip it toggles between 0 volts and the 8-bit D level.
PPS: The four %VV options of DAC drive strength are available to BIT_DAC mode.
Yeah thats the mode. But I think the DDDDDDDD were repurposed so that 4 bits each set the high and low level, rather than high setting an 8 bit level, and low being always 00000000
I guess this first HDMI test example simply uses 3.3V logic levels for now. In time it will be good to see if the pin settings for differential voltages and impedances compatible with CML do fully work with it too. I think some of that was discussed in another thread (probably that long HDMI one). It's fabulous to see the internal TMDS encoding and streamer change is working, regardless of the analog side.
There's a pin mode that uses the dacs to drive the digital output pin, the advantage being both the absolute High level and Low level can be one of 16 values (0.0 through 3.3v) , so it should be possible to do something approaching CML
Be interesting to try, but can the DAC's mange 250MHz ? I'd expect a CMOS pin to settle faster, and so give a better eye pattern.
I guess this first HDMI test example simply uses 3.3V logic levels for now. In time it will be good to see if the pin settings for differential voltages and impedances compatible with CML do fully work with it too. I think some of that was discussed in another thread (probably that long HDMI one). It's fabulous to see the internal TMDS encoding and streamer change is working, regardless of the analog side.
There's a pin mode that uses the dacs to drive the digital output pin, the advantage being both the absolute High level and Low level can be one of 16 values (0.0 through 3.3v) , so it should be possible to do something approaching CML
Be interesting to try, but can the DAC's mange 250MHz ? I'd expect a CMOS pin to settle faster, and so give a better eye pattern.
That digital outputs are 20 ohm impedance, while the lowest impedance DAC output is 75 ohms.
I guess this first HDMI test example simply uses 3.3V logic levels for now. In time it will be good to see if the pin settings for differential voltages and impedances compatible with CML do fully work with it too. I think some of that was discussed in another thread (probably that long HDMI one). It's fabulous to see the internal TMDS encoding and streamer change is working, regardless of the analog side.
There's a pin mode that uses the dacs to drive the digital output pin, the advantage being both the absolute High level and Low level can be one of 16 values (0.0 through 3.3v) , so it should be possible to do something approaching CML
Be interesting to try, but can the DAC's mange 250MHz ? I'd expect a CMOS pin to settle faster, and so give a better eye pattern.
I was pumping out pixels earlier today at 380MHz with no signs of trouble. The chip was barely warm.
In this last silicon iteration, we grouped the pins' IN and OUT timings so that all INs propagate from the pins to the core flops within 1ns of eachother and all OUTs propagate from the core flops to the pins within 1ns of eachother.
That digital outputs are 20 ohm impedance, while the lowest impedance DAC output is 75 ohms.
75 ohms source impedance may still be okay and could be worth a try, though 50 ohms is the ideal I think to keep everything matched to avoid extra reflections. The problem right now may be that the total swing is a bit too large if driven all the way from 0V to 3.3V and this could possibly affect the CML receivers. The operating DC differential signal at the sink itself is meant to be kept under 1.2V, which for each single ended signal I think means seeing voltages no less than 600mV below the 3.3V termination bias voltage at the receiver. Another part of the DVI spec I read mentions the maximum differential swing is 1.56V for AC signals.
Some quick back of envelope calculations show that you might like to drive the DVI/HDMI pins from (something above) 1.8V through to 3.3V DAC levels at 75 ohms source impedance to yield less than 600mV single ended swing into 50 ohms via the transmission line. However any overshoot and undershoot ringing due to parasitics and reflections from impedance mismatch etc can affect the AC levels reached as well, so even less swing might be needed.
Comments
Here's the tests and photos from when we were trying to exacerbate and measure (via photos) the pll wobbles.
We were driving single color (green) VGA at 2048 x 1536 into a Rogloh's Sony G20 monitor.
I think the dot clock was 210 MHz, using "Vesa RB1" blanking standard. I don't think the monitor supported the Vesa RB2 standard.
In addition, we needed to cycle things up and down using a halogen floodlight as a kind of gentle radiator. The wobbles were somewhere around 20 or 30 degrees above the free air natural temp of the prop (ie the additional heat was required to bring them on)
I don't think we had many cogs running, but I'm sure it wouldn't hurt.
https://forums.parallax.com/discussion/comment/1462193/#Comment_1462193
Thank you so much. To make me feel ancient.
Same here. Can we pre-pay/order boards?
Once they become available, we'll have enough for everyone who wants one.
Here's the code that displays the image:
'******************************************** '* VGA 640 x 480 x 16bpp 5:6:5 RGB - HDMI * '******************************************** CON hdmi_base = 8 DAT org ' ' ' Setup ' hubset ##%1_000001_0000011000_1111_10_00 'configure PLL, 20MHz / 2 * 25 * 1 = 250MHz waitx ##20_000_000 / 200 'allow crystal and PLL 5ms to stabilize hubset ##%1_000001_0000011000_1111_10_11 'switch to PLL rdfast ##640*350*2/64,##$1000 'set rdfast to wrap on bitmap setxfrq ##$0CCCCCCC+1 'set transfer frequency to 1/10th clk, +1 for initial rollover setcmod #$100 'enable HDMI drvl #7<<6 + hdmi_base 'enable HDMI pins ' ' ' Field loop ' field mov hsync0,sync_000 'vsync off mov hsync1,sync_001 callpa #90,#blank 'top blanks mov x,##350 'set visible lines line call #hsync 'do horizontal sync xcont m_rf,#1 'do visible line djnz x,#line 'another line? callpa #83,#blank 'bottom blanks mov hsync0,sync_222 'vsync on mov hsync1,sync_223 callpa #2,#blank 'vertical sync blanks jmp #field 'loop ' ' ' Subroutines ' blank call #hsync 'blank lines xcont m_vi,hsync0 _ret_ djnz pa,#blank hsync xcont m_bs,hsync0 'horizontal sync xzero m_sn,hsync1 _ret_ xcont m_bv,hsync0 ' ' ' Initialized data ' sync_000 long %1101010100_1101010100_1101010100_10 ' sync_001 long %1101010100_1101010100_0010101011_10 ' hsync sync_222 long %0101010100_0101010100_0101010100_10 'vsync sync_223 long %0101010100_0101010100_1010101011_10 'vsync + hsync m_bs long $7F910000+16 'before sync m_sn long $7F910000+96 'sync m_bv long $7F910000+48 'before visible m_vi long $7F910000+640 'visible m_rf long $BF950000+640 'visible rfword rgb16 (5:6:5) ' ' ' Uninitialized data ' x res 1 hsync0 res 1 hsync1 res 1 ' ' ' Bitmap ' orgh $1000 - 70 'justify pixels at $1000 file "birds_16bpp.bmp" 'rayman's picture (640 x 350)Totally freakin awesome! Very :cool:
Impressive, and impressively compact code - but needs more comments for users to follow what P2 is doing here.
With ASM examples, I like to include a comment appendix that shows
; Build command lines
; Code Size reports
; % CPU used for the example, here that would be COG cycles spare
Maybe the adapter board Chip is using, includes those ?
Chip,
When i was seeing jitter/shimmering I was dividing the input xtal/osc to give 0.5MHz and then multiplying that up. This was on VGA 1920x1080. As i am away, perhaps you can try this???
So this needs retesting. Unfortunately I won’t be back in Oz until 25th Aug. While i have my P2D2 with me, i don’t have access to a VGA 1920x1080 monitor here.
Chip has tested lots of configs, including more extreme configurations, on this v2 chip. None show any shimmering.
Err, sorry, maybe he hasn't tested higher resolutions at all. A high resolution mode with a selection of different dividers would be a good idea.
There's a pin mode that uses the dacs to drive the digital output pin, the advantage being both the absolute High level and Low level can be one of 16 values (0.0 through 3.3v) , so it should be possible to do something approaching CML
PS: It has changed in the v2 chip to two 4-bit levels. With the v1 chip it toggles between 0 volts and the 8-bit D level.
PPS: The four %VV options of DAC drive strength are available to BIT_DAC mode.
Be interesting to try, but can the DAC's mange 250MHz ? I'd expect a CMOS pin to settle faster, and so give a better eye pattern.
That digital outputs are 20 ohm impedance, while the lowest impedance DAC output is 75 ohms.
I was pumping out pixels earlier today at 380MHz with no signs of trouble. The chip was barely warm.
In this last silicon iteration, we grouped the pins' IN and OUT timings so that all INs propagate from the pins to the core flops within 1ns of eachother and all OUTs propagate from the core flops to the pins within 1ns of eachother.
75 ohms source impedance may still be okay and could be worth a try, though 50 ohms is the ideal I think to keep everything matched to avoid extra reflections. The problem right now may be that the total swing is a bit too large if driven all the way from 0V to 3.3V and this could possibly affect the CML receivers. The operating DC differential signal at the sink itself is meant to be kept under 1.2V, which for each single ended signal I think means seeing voltages no less than 600mV below the 3.3V termination bias voltage at the receiver. Another part of the DVI spec I read mentions the maximum differential swing is 1.56V for AC signals.
Some quick back of envelope calculations show that you might like to drive the DVI/HDMI pins from (something above) 1.8V through to 3.3V DAC levels at 75 ohms source impedance to yield less than 600mV single ended swing into 50 ohms via the transmission line. However any overshoot and undershoot ringing due to parasitics and reflections from impedance mismatch etc can affect the AC levels reached as well, so even less swing might be needed.