Memory Breakout Poll

VonSzarvasVonSzarvas Posts: 1,543
edited 2019-06-18 - 18:12:18 in Propeller 2
I'd just started looking at a small volatile and/or non-volatile breakout for P2, and the forum is showing me lots of hits on the topic!

Seems to me, this could be done quickly and ready for ordering with the new RevB EVAL board.

But I need some help, and it's obvious so many of you are already experts on what type of memory you'd like.


What's the minimum speed, latency, etc, which would be useful.
SPI seems like the protocol to go for, and either multiple memory chips of one type, or "some of each".

Assuming a dual card, that's 16 I/O's up for grabs. The memory should operate at 3.3V

If there's a spare I/O, we could add a serial number - maybe: DS2411R+T&R

Realistically only parts that are currently in-stock at the usual distros could be considered.


One part that stood out was :
FLASH - NAND Memory IC 1Gb (128M x8) SPI - Quad I/O 120MHz 8-WSON (6x8), 3V3,
https://www.digikey.com/product-detail/en/gigadevice-semiconductor-hk-limited/GD5F1GQ4UFYIGR/1970-1081-1-ND/9484830

wow!


Please vote on your favorites!
(Especially volatile parts, considering throughput)
«1345

Comments

  • VonSzarvas, this is also about HyperRAM, right?
  • Yes, HyperRAM and possibly some sort of HyperFLASH.

    Or whatever else cool name the latest and greatest fast access serial memories are called.
  • I'd like core memory.
  • David Betz wrote: »
    I'd like core memory.

    Do you mean fast volatile memory, much like a PC would have ?
    What sort of capacity ?

    How would you imagine managing that.... a memory cog perhaps, that manages the expansion memory card and provides a conduit to hub?
  • David BetzDavid Betz Posts: 13,343
    edited 2019-06-18 - 20:47:29
    VonSzarvas wrote: »
    David Betz wrote: »
    I'd like core memory.

    Do you mean fast volatile memory, much like a PC would have ?
    What sort of capacity ?

    How would you imagine managing that.... a memory cog perhaps, that manages the expansion memory card and provides a conduit to hub?
    No, I want those little magnetic donuts wired in a 2D array. You know, the ones they used to have in my old PDP-10! :smile:

    Sorry, it was a dumb joke.

  • David, I have one board left but I don't think I can interface it up to an accessory board.

    Maybe a Intel 1702 instead? That should fit. :)
    1024 x 544 - 351K
    Infernal Machine
  • I personally would like to see a dual HyperRam configuration. The guys have been bumping up against the limits with HyperRAM… so doubling up would not only provide twice the memory but also either a 16-bit path or 2 asynchronous 8 bit paths.


    No matter what you decide... it is going to be a very popular little board:)
  • Publison wrote: »
    David, I have one board left but I don't think I can interface it up to an accessory board.

    Maybe a Intel 1702 instead? That should fit. :)
    Yup! That's what I want. However, as you say, it may not fit on an accessory board.

  • jmgjmg Posts: 13,611
    VonSzarvas wrote: »
    Please vote on your favorites!
    (Especially volatile parts, considering throughput)

    You could allow for this ?
    https://lcsc.com/product-detail/RAM_Lyontek-Inc-LY68L6400SLIT_C261881.html
    That's like HyperRAM, but in SO8n, 4 bits wide. Has similar refresh rules. I think that's a standard SO8 RAM,
    so it would also suit the newest Larger/faster Static SRAM parts like
    IS62WVS5128GBLL x1, x2, x4 2.7~3.6V 45MHz -40 to 125°C 8-SOIC Prod Serial SRAM

    One question is do you add 2 of those, to allow x8 read, and so even more like HyperRAM.
    Once someone has a PCB done and used pins for HyperFLASH BGA x8, they may decide to use pairs of those SO8 RAMs ?

  • cgraceycgracey Posts: 11,272
    edited 2019-06-18 - 23:03:02
    jmg wrote: »
    VonSzarvas wrote: »
    Please vote on your favorites!
    (Especially volatile parts, considering throughput)

    You could allow for this ?
    https://lcsc.com/product-detail/RAM_Lyontek-Inc-LY68L6400SLIT_C261881.html
    That's like HyperRAM, but in SO8n, 4 bits wide. Has similar refresh rules. I think that's a standard SO8 RAM,
    so it would also suit the newest Larger/faster Static SRAM parts like
    IS62WVS5128GBLL x1, x2, x4 2.7~3.6V 45MHz -40 to 125°C 8-SOIC Prod Serial SRAM

    One question is do you add 2 of those, to allow x8 read, and so even more like HyperRAM.
    Once someone has a PCB done and used pins for HyperFLASH BGA x8, they may decide to use pairs of those SO8 RAMs ?

    That's a pretty neat part. Inexpensive, too.
  • When jmg posted that linked I checked it out and I really want to build it into my next P2D2. A whopping 8MBs of RAM and I only need 6 I/O altogether for QSPI although I could probably share some.
    Maybe I should allow for a pair of them for full 8-bit wide data and 16MB.

    The price is secondary to the fact that they are 8-pin easy to use SOIC, but the low cost sure puts icing on the cake!

    Tachyon Forth - compact, fast, forthwright and interactive
    useforthlogo-s.png
    --->CLICK THE LOGO for more links<---
    P2 +++++ TAQOZ INTRO & LINKS +++++ P2 SHORTFORM DATASHEET
    P1 +++++ Latest binary V5.4 includes EASYFILE +++++ Tachyon Forth News Blog
    Brisbane, Australia
  • Seems like we should be able to substitute the Flash with the LY68L6400 part which is what I will try on my P2D2 since I use the SD for boot. I'm in the process of ordering some of these now.
    There's a possibility that accessing the SD may interfere with self-refresh but the SD clock normally idles high since it is also the Flash CE.

    Tachyon Forth - compact, fast, forthwright and interactive
    useforthlogo-s.png
    --->CLICK THE LOGO for more links<---
    P2 +++++ TAQOZ INTRO & LINKS +++++ P2 SHORTFORM DATASHEET
    P1 +++++ Latest binary V5.4 includes EASYFILE +++++ Tachyon Forth News Blog
    Brisbane, Australia
  • @Peter Jakacki I hope this RAM stuff won't derail the current P2D2R2...? Each time more IO pins get eaten up by new P2D2 features I may start to need to alter my board and am guessing I may soon start to lose functionality. It would be good to keep certain features optional to maximize IO availability on a "base" P2D2 version.
  • I like the potential of HyperRAM because it is DDR. The down sides to HyperRAM specifically are it's single sourced and has only the one painful packaging type.

    DDR with the Propeller2: Because the fastest external bus clock a prop can emulate is 1/2 sysclock, DDR presents the possiblility to go all the way to sysclock data rates. Although I don't know how viable, timing wise, this line of thinking actually is.

    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • rogloh wrote: »
    @Peter Jakacki I hope this RAM stuff won't derail the current P2D2R2...? Each time more IO pins get eaten up by new P2D2 features I may start to need to alter my board and am guessing I may soon start to lose functionality. It would be good to keep certain features optional to maximize IO availability on a "base" P2D2 version.

    Don't worry, if I do have a dual version for an 8-bit bus then it will be on a sandwich pcb, not the P2D2 itself. But it seems I can replace the Flash with one of these to gain 8MB of RAM!

    Tachyon Forth - compact, fast, forthwright and interactive
    useforthlogo-s.png
    --->CLICK THE LOGO for more links<---
    P2 +++++ TAQOZ INTRO & LINKS +++++ P2 SHORTFORM DATASHEET
    P1 +++++ Latest binary V5.4 includes EASYFILE +++++ Tachyon Forth News Blog
    Brisbane, Australia
  • koehler wrote: »

    Not suitable for the prop. That stuff is manufactured to act like DRAM, for DDR4 DIMMs. All the same control lines and paging and buffering, except devoid of the refresh cycles. The pin count is way high and the voltages are way low. MRAM DDR3 parts exist on the market at 1.5 volts. DDR4 is nominally 1.2 volts.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • An external RAM controller (FPGA maybe) with level translation built in would make DDR3/4 parts viable.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • YanomaniYanomani Posts: 850
    edited 2019-06-19 - 05:07:41
    evanh wrote: »
    I like the potential of HyperRAM because it is DDR. The down sides to HyperRAM specifically are it's single sourced and has only the one painful packaging type.

    DDR with the Propeller2: Because the fastest external bus clock a prop can emulate is 1/2 sysclock, DDR presents the possiblility to go all the way to sysclock data rates. Although I don't know how viable, timing wise, this line of thinking actually is.

    In order to reach those speeds (HyperD[7:0] -> @Sysclk; HyperCK -> @Sysclk/2), we would need that the falling/leading edges of HyperCK could occur near the vicinity of the falling edge of Sysclk, wich is not possible at the current design, since it uses the leading edge of Sysclk to latch the incoming/outcoming signals, to/from the pins.

    Better yet, if we could dinamically select between 90º, 180º and 270º phases, relative to Sysclk leading edge.

    If we could sport those options, along with carefull layout, and knowing the exact margins for setup and hold times, both for incoming (to P2 pins) and outcoming (from P2 pins) signals, we could eventually dream with up-to 200 MB/s transfer rates (per HyperRam, @3.3 V).

    P2 overclocking till 400 MHz isn't feasible. Frying bits, anyone?

    We could eventually try overclocking it till 332 MHz, to reach 166 MB/s, but it's not a great deal, given we'll loose HDMI @ 250 MHz compatibility.

    Going the 1.8 V, voltage-translation route is not an option, due to the involved costs and also due HDMI-compatibility concerns, beyound 250 MHz.

    Now, if you want to talk about designing a twin-P2 (2-P2??) EVAL, with ~64 free Smart Pins, lots of HyperRams (or eight-pin QPIs) (or mixed Flash/Ram), with plenty of HDMI/VGA options, serving almost every taste, I'm in and ready!

    Just ask yourself why two P2, (and how).... :smile:

    Henrique

    P.S. As for HyperFlash and HyperRam sources, there are two at least: Cypress and ISSI.
  • What the spec says and what can be achieved aren't always the same.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • BGA for small packages is stupid.
    "... peers into the actual workings of a quantum jump for the first time. The results
    reveal a surprising finding that contradicts Danish physicist Niels Bohr's established view
    —the jumps are neither abrupt nor as random as previously thought."
  • OT here but I can't resist.

    I'm with Henrique: "Now, if you want to talk about designing a twin-P2 (2-P2??) EVAL, with ~64 free Smart Pins, lots of HyperRams (or eight-pin QPIs) (or mixed Flash/Ram), with plenty of HDMI/VGA options, serving almost every taste, I'm in and ready!"

    Answer to complex queries to your office:
    "U can do it with a P2, but you might need more than one"

    Peter
    I agree with everyone else... get the P2D2V2 in the wild and don't let anything slow you. But when you are dreaming about what might come after that... think about a !P2!3D!. Imagine a Rubik's cube of P2's... that's what Santa wants from your workshop.

    Question:
    "But how do I hook up more than 1 P2s?"

    Answer:
    "You kind of slap them together... Have you ever seen a Rubik's cube? Same Idea without the moving parts."



  • In fact, two are enough, to match 200 MB/s transfer rate per HyperSomething chip, @ 3.3 V.

    That's why I've suggested two P2 at the same pcb.

    For a long time now, I've beem dreaming to put my hands on an affordable 64-channel logic/protocol analyzer. Add some scope modes and function generator options too. Two P2 can do it, nicely.

    My old (1990) 40 MHz dual channel scope is deadly broken, full of salt crystals and dust. It needs a grave!
  • With the streamer I may can currently move 1-2-4-8-16 or 32 bits at sys clock/2 from one P2 to the other (if I had two of them). Maybe sys clock/3 because of phase difference of two clock sources. Like others I dream of a rubic cube P2.

    I am silently hoping @Cluso99 will do a small 4 P2 board, but I am also hoping for a while now that he re-runs his ram-blade(?) so that I could finally run CP/M on the P1.

    @pullmoll left some years ago, @heater does not want to write emulators anymore (and seems to be MIA also), but somebody started a Z80 emulation, so there is hope for CP/M on the P2 at reasonable speed.

    Generally I like @Peter Jakacki's P2D2 concept more then the big P2-eval, having a pre-made module to plug into extension boards could even allow me to 'design' such.

    Catalina seems to still support XMM on the P1, maybe @RossH can/will support something like that on the P2 version too. PropGcc seems to have dropped XMM, PropGcc2 is not in the planning, yet.

    But generally having external RAM at reasonable speed would be very nice to have.

    Mike
    I am just another Code Monkey.
    A determined coder can write COBOL programs in any language. -- Author unknown.
    Press any key to continue, any other key to quit

    The key words "MUST", "MUST NOT", "REQUIRED", "SHALL", "SHALL NOT", "SHOULD", "SHOULD NOT", "RECOMMENDED", "MAY", and "OPTIONAL" in this post are to be interpreted as described in RFC 2119.
  • msrobots wrote: »
    PropGcc seems to have dropped XMM, PropGcc2 is not in the planning, yet.
    All versions of PropGCC support XMM. It's SimpleIDE that dropped support for XMM. If you want to use XMM with PropGCC you'll have to compile from the command line.

  • @Peter Jakacki wrote:
    When jmg posted that linked I checked it out and I really want to build it into my next P2D2. A whopping 8MBs of RAM and I only need 6 I/O altogether for QSPI although I could probably share some.
    Maybe I should allow for a pair of them for full 8-bit wide data and 16MB.
    

    Hey, it seems there was some guy on the Prop1 forum who was wanting to add memory to a Prop1 board and was taken to task over it. I guess the desire for additional memory isn't limited to the Prop1 platform :)

    On a more serious note, I understand why @RossH is a little reluctant on committing to this feature for Catalina, and @David Betz , @Jazzed, and others for the PropGCC.

    A plethora of boards and memory configurations and their variants creates a nightmare for the Compiler developers.

    Maybe it's time for a "Working Group" blessed by Parallax to come up with standard memory arrangements for the Prop2 that will be supported by the Compilers?

    Maybe have a standardized layout for parallel memory and another for serial SPI/SQI?

    Imagine if each Compiler only had to account for one parallal memory design and one serial memory design, with variants as to which pins can used for each respective design, but the memory architecture for each memory type is fixed.

    Thoughts?
  • On a more serious note, I understand why @RossH is a little reluctant on committing to this feature for Catalina, and @David Betz , @Jazzed, and others for the PropGCC.
    Well, there is currently no work being done on PropGCC2 as far as I know and jazzed is pretty much gone. However, Eric's fastspin C compiler is making good progress as is Catalina so maybe we don't need PropGCC2.

  • You know, I haven't looked at Eric's FastSpin C compiler yet.

    I've only been concentrating on Catalina, with PropGCC as runner up.

    Any idea if FastSpin supports XMM mode on the Prop1? If so, I need to take it look at it as well.
  • You know, I haven't looked at Eric's FastSpin C compiler yet.

    I've only been concentrating on Catalina, with PropGCC as runner up.

    Any idea if FastSpin supports XMM mode on the Prop1? If so, I need to take it look at it as well.

    No, fastspin doesn't (yet) support XMM mode. There's a partial implementation of CMM mode, but it's probably going to be a few weeks before that's stable enough to use regularly.

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