How do smartpin DAC modes work?

twm47099 · 2019-05-21 02:59

I am trying to understand the smartpin DAC mode, but have not been very successful.
Assume that I want to output a specific voltage 0.5 to 3.0V on a specific pin. I would want to use one of the DAC modes, but

What is the difference between the 3 modes? (How would I decide which to use?)
What are the values for the following commands?
wrpin
wxpin
wypin

The documentation states that %DDDDDDDD = DAC level.
How do I calculate %DDDDDDDD from the desired voltage? (for example 2.5v = ??)

An example would be appreciated.

The documentation states that %TT “for DAC smart pin modes (%MMMMM = %00001..%00011):
0x = OUT enables ADC in DAC_MODE, P[7:0] overriden
1x = OTHER enables ADC in DAC_MODE, P[7:0] overridden”

How is ADC being used in the DAC modes (I’m completely confused by this. Does it mean I can use the DAC mode to do ADC instead of using the sigma delta smartpin mode? How?)

I appreciate your help, and I know I will have more questions.

Thanks
Tom

Tubular · 2019-05-21 03:04

check out the late posts in this thread with same issue
http://forums.parallax.com/discussion/170060/smart-pin-dac#latest

its the wrpin and enable you need to wrangle, they aren't true smartpin modes so no wxpin nor wypin required

look forward to the other questions

evanh · 2019-05-21 05:09

There's a few different ways to control the DACs:
- Direct setting the level in the pin config. (DAC_MODE)
- Comparator preset level. (COMP_DAC)
- OUT toggling between two levels. (BIT_DAC)
- Smartpin modes 1,2 and 3. Modes 2 and 3 extend to 16-bit with an 8-bit dither. (SMART_DAC)
- Cog SETDACS channels and streamer DAC channels. (COG_DAC)

That's eight configurable ways to chose from for each DAC.

PS: I wouldn't be surprised if I've missed one. PPS: Yes, I suspect, all the smartpin and streamer data can be used with the comparator too. So that's another five odd theoretical choices.

Tubular · 2019-05-21 05:39

Just on your other questions, there are 256 DAC levels between 0 and 3v3, so 12.941mV per step. To get 2.5v you'd use code 2.5/3.3*255=193.

Regarding using the ADC at the same time as the DAC, this is a special feature that can turn on the ADC and measure the external load experienced by the DAC. It will come in handy for things like detecting connected monitors and devices, current drawn by external circuits, etc.

twm47099 · 2019-05-21 06:10

Tubular wrote: »

Just on your other questions, there are 256 DAC levels between 0 and 3v3, so 12.941mV per step. To get 2.5v you'd use code 2.5/3.3*255=193.

Regarding using the ADC at the same time as the DAC, this is a special feature that can turn on the ADC and measure the external load experienced by the DAC. It will come in handy for things like detecting connected monitors and devices, current drawn by external circuits, etc.

Thanks for the info.
Do the smart pin DAC modes 00010 (16-bit with pseudo-random dither) and 00011 (16-bit with PWM dither) have 65,535 voltage steps? Or am I not understanding the title of the modes?

Regarding the ADC with the DAC, is the ADC read on a different pin than the DAC?

cgracey · 2019-05-21 06:19

twm47099 wrote: »

Tubular wrote: »

Just on your other questions, there are 256 DAC levels between 0 and 3v3, so 12.941mV per step. To get 2.5v you'd use code 2.5/3.3*255=193.

Regarding using the ADC at the same time as the DAC, this is a special feature that can turn on the ADC and measure the external load experienced by the DAC. It will come in handy for things like detecting connected monitors and devices, current drawn by external circuits, etc.

Thanks for the info.
Do the smart pin DAC modes 00010 (16-bit with pseudo-random dither) and 00011 (16-bit with PWM dither) have 65,535 voltage steps? Or am I not understanding the title of the modes?

Regarding the ADC with the DAC, is the ADC read on a different pin than the DAC?

The 16-bit DAC modes dither the 8-bit DAC between two adjacent levels. Actually, unique output values range from $0000..$FF00. The last 255 steps don't exist because the 8-bit DAC can't go higher than $FF. There's no 'next' level to dither to. So, there are $10000-$FF output levels possible, which amount to 65,281, yielding a step size of 50.55uV (3.3V / 65,821).

The ADC and DAC can operate simultaneously on the SAME pin.

evanh · 2019-05-21 08:58

cgracey wrote: »

twm47099 wrote: »

Regarding the ADC with the DAC, is the ADC read on a different pin than the DAC?

The ADC and DAC can operate simultaneously on the SAME pin.

Short answer is yes. The smartpin can only do one job at a time.

The smartpins are somewhat loosely tied to the physical pins. Each physical pin has one ADC, one DAC and one associated smartpin. If you want to use the smartpin to control the DAC, and the ADC to also go to a smartpin then the ADC would have to be directed to a neighbouring smartpin. A streamer can run the ADC though.

Or the DAC can be run from a streamer or cog. Then the smartpin can run the ADC without using another smartpin.

evanh · 2019-05-21 09:26

Prop2 definitely needs block diagrams far more than the Prop1 did. Sadly, that's something I'm way unskilled on.

cgracey · 2019-05-21 10:34

The 16-bit DAC smart pin modes can sum up ADC bits within the update period. At the end of each period, you can give it a new 16-bit output sample and pick up the ADC reading from the period that just finished. No need for extra pins.

evanh · 2019-05-21 10:47

Really? Cool, that's a good trick but must be bulking up the smartpin.

evanh · 2019-05-21 11:28

Here's my latest ASCII block diagram (Still doesn't have the DAC channels though)

                                                    Other ---------------------------------------- RND
                                                         |
                                                         v
                                                   [=============]          [============]
                                                   [             ]          [  (M == 0)  ]
                                                   [ Logic Output]<---------[---o----o---]<------- DIR
                         [=============]   DIR     [  Config     ]          [            ]
                         [  Pin Output ]<----------[  (%TT)      ]          [  (M == 0)  ]
[========]               [  Config     ]   OUT     [             ]<---------[---o----o---]<------- OUT
[        ]<--------------[  (%P...P)   ]<--+-------[             ]          [            ]
[Physical]               [=============]   |       [=============]          [            ]
[  Even  ]                   ^             |                                [   Even #   ]
[  Pin   ]                   |             |                                [  Smartpin  ]
[        ]------             |             |         -1  -2  -3             [   Config   ]
[========]      |            |             |          |   |   |             [ (%MMMMM_0) ]
                |            |             |          v   v   v             [            ]
                |            |             |       [=============]      A   [            ]
                |  PinB  [=============]    ------>[ Logic Input ]--------->[---o----o---]--------> IN
              ---------->[  Pin Input  ]           [   Config    ]      B   [  (M == 0)  ]
             |  |  PinA  [  Config     ]---------->[  (%A_B_F)   ]--------->[            ]
             |  +------->[  (%P...P)   ]           [=============]          [            ]
             |  |        [=============]              ^   ^   ^             [============]
             |  |                                     |   |   |
             |  |                                     |   |   |
             |  |                                    +1  +2  +3
             |  |
             |  |
             |  |
             |  |                         Other    [=============]          [============]
             |  +--------------------------------->[             ]          [  (M == 0)  ]
             |  |                                  [ Logic Output]<---------[---o----o---]<------- DIR
             |  |        [=============]   DIR     [  Config     ]          [            ]
             |  |        [  Pin Output ]<----------[  (%TT)      ]          [  (M == 0)  ]
[========]   |  |        [  Config     ]   OUT     [             ]<---------[---o----o---]<------- OUT
[        ]<--------------[  (%P...P)   ]<--+-------[             ]          [            ]
[Physical]   |  |        [=============]   |       [=============]          [            ]
[  Odd   ]   |  |            ^             |                                [   Odd #    ]
[  Pin   ]   |  |            |             |                                [  Smartpin  ]
[        ]---+  |            |             |         -1  -2  -3             [   Config   ]
[========]   |  |            |             |          |   |   |             [ (%MMMMM_0) ]
             |  |            |             |          v   v   v             [            ]
             |  |            |             |       [=============]      A   [            ]
             |  |  PinB  [=============]    ------>[ Logic Input ]--------->[---o----o---]--------> IN
             |   ------->[  Pin Input  ]           [   Config    ]      B   [  (M == 0)  ]
             |     PinA  [  Config     ]---------->[  (%A_B_F)   ]--------->[            ]
              ---------->[  (%P...P)   ]           [=============]          [            ]
                         [=============]              ^   ^   ^             [============]
                                                      |   |   |
                                                      |   |   |
                                                     +1  +2  +3

Edit: Added Odd/Even vs PinA/PinB routing.

cgracey · 2019-05-21 11:51

evanh wrote: »

Really? Cool, that's a good trick but must be bulking up the smartpin.

It was mostly free to add the ADC summing.

Man, we need some nice way to make block diagrams.

Yanomani · 2019-05-21 12:58

When it comes for block diagrams and apart from any other solutions anyone can point to, there are at least two open-source softwares one can rely.

Both Libre Office Draw and Pencil Project (https://pencil.evolus.vn/) has a nice set of features and are actively maintained by their respective communities.

If yet unknown to many, perhaps some could try one or both and report back their personal opinions about them.

Hope it helps

Henrique

evanh · 2019-05-21 13:14

I've tried Draw, the flowchart tools don't suit. I guess sketching everything similar to the ASCII art can be done with it.

Yanomani · 2019-05-21 13:34

Hi evanh

As for LibreOffice Draw, perhaps you can try Mark Lautman's freely available logic gates and electrical engineering/schematic drawing shapes. I believe they'll mostly suit all the needs, without having to rely on text-derived shapes.

lautman.net/mark/coo/index.html

Hope it helps

Henrique

evanh · 2019-05-21 14:14

Okay, Pencil looks much more suitable. It's certainly got its limitations but the flowchart part works notably better than Draw's version. I can make clear joins/branches in the lines that are links to the process boxes and therefore the objects can be dragged like schematic parts for easy shuffling of position.

evanh · 2019-05-21 14:28

Yanomani wrote: »

As for LibreOffice Draw, perhaps you can try Mark Lautman's freely available logic gates and electrical engineering/schematic drawing shapes.

It would be nice to have both in one package but for logic snippets I'll use PCB schematic software I think. That allows easy rearrangement that maintains the nets.

Yanomani · 2019-05-21 14:48

Good to know that Pencil Project's features has shown to be useful to you.

When I'm in a hurry and wanna only the visual results, says, to clarify some point, I tend to rely on Digikey's SchemeIt for schematics. It mostly spares me from creating/searching for a lot of shapes and package drawings and works right there in my preferred browser (Firefox).

whicker · 2019-05-21 16:08

Visio works great for technical block diagrams once you understand its underlying behavior and stay on a consistently sized grid.
Connector lines want to join to Connection Points on Shapes.
Pick a good font and size (8 point is good) and a good line weight and stick to that style.

The hardest part of the learning curve is to understand snap & glue and know what to turn off. Page Auto Size being the very first thing you turn off.

I am not knocking my suggestion and I think Visio is very good for block diagrams, but in the newer version the arrangement of the Ribbon makes it seem more confusing than it needs to be. Visio 2007 and 2010 was basically perfect in terms of what was shown, and what was accessible from a dropdown menu on top. It's still manageable and you can put a bunch of commonly used functions back on the "Quick Access Toolbar" instead of flipping thru ribbon tabs.

Cluso99 · 2019-05-26 01:21

ExpressSCH is an easy to use schematic software and is free.
Creating blocks of any size is easy.
Duplicating sections. Draw lines or draw connections, etc.
Comes with a base library and is easy to create your own using an existing one as a base, or from scratch.

evanh · 2019-05-26 02:41

The connections to each block ideally are dynamic in number. Pencil allows up to 8 per block so should work out quite good.

At this stage I'm on other projects again so will be some time before getting back to it.

How do smartpin DAC modes work?

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