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What is the maximum current that each pin can source? — Parallax Forums

What is the maximum current that each pin can source?

samuellsamuell Posts: 554
edited 2019-05-17 23:26 in Propeller 2
Hi,

What is the maximum current that each pin can source? And conversely, what is the maximum current each one can sink? I'm asking this because I've modified the prototyping board to light one LED per output. I've used 82R resistors, which gives roughly 14mA for the green LEDs I'm using. Is that too much?

Kind regards, Samuel Lourenço

Comments

  • cgraceycgracey Posts: 14,153
    30mA would be a conservative rating.
  • samuellsamuell Posts: 554
    That is nice to know Chip. Thanks!

    Kind regards, Samuel Lourenço
  • Peter JakackiPeter Jakacki Posts: 10,193
    edited 2019-05-18 05:55
    While we are on that subject normally there is a maximum that applies to a group of pins or the whole chip. You wouldn't have 64 pins sourcing 30ma each for instance. What is that?
  • cgraceycgracey Posts: 14,153
    edited 2019-05-18 05:56
    Peter Jakacki wrote: »
    While we are on that subject normally there is a maximum that applies to a group of pins or the whole chip. You wouldn't have 64 pins sourcing 30ma each for instance. What is that?

    We designed things very conservatively regarding power delivery. For every four I/O pins, there is a GND and a VIO bond wire that are each 1mil diameter gold, which have about 1A capacity for their 1mm length. The top metal layer of the chip (M6) is 3um thick and used as the power grid on the die.
  • evanhevanh Posts: 15,916
    32 Amps total then. :D
  • cgraceycgracey Posts: 14,153
    edited 2019-05-18 06:55
    evanh wrote: »
    32 Amps total then. :D

    Well, those GND and VIO wires are in series, effectively, so only 16 Amps. I think the bond wires have much greater capacity than the GND and VIO pads they connect to.
  • evanhevanh Posts: 15,916
    I'm counting the core too. Lol, I wasn't being serious.
  • cgraceycgracey Posts: 14,153
    evanh wrote: »
    I'm counting the core too. Lol, I wasn't being serious.

    Yes, the core power connections would make it 32 Amps. We won't have a wiring problem.
  • jmgjmg Posts: 15,173
    Usually MCUs are thermally defined on IO ratings.
    Taking the 30mA mentioned already, over a hypothetical 60 pins (getting quite rare) that's 1.80 Amps (tolerable, with that many pins bonded), and at a nominal 10 ohms FETs that is 0.54W added from the IO i2r effects alone
    That's more of a factor to consider - it might be enough to bump a design from 2L to 4L for example, depending on target MHz.
  • Peter JakackiPeter Jakacki Posts: 10,193
    So the 2A switcher I have on my P2D2 is way under-rated then? :) But so is the copper.

    Because of this I may stress test a P2 chip if I'm game, at least up to 2A. Isn't there a problem with too much current flowing through the substrate and the resultant voltage drop/rise?
  • jmgjmg Posts: 15,173
    Peter Jakacki wrote: »
    So the 2A switcher I have on my P2D2 is way under-rated then? :) But so is the copper.
    Depends where the load current comes from :)
    You could, for example drive Blue LEDs to a 5V rail from P2 pins, and not have any additional SMPS load.
    Peter Jakacki wrote: »
    Because of this I may stress test a P2 chip if I'm game, at least up to 2A. Isn't there a problem with too much current flowing through the substrate and the resultant voltage drop/rise?
    The PAD ring has the bonding pads, and the wide metal, so most of the drop is across the mosfet, but you probably can measure some millivolts across the metal on groups of 4 IOs, if you look for them.
    You can also load 3 pins, and just CMOS out the 4th, to read the internal GND potential shift, caused by those 3 loaded pins.

  • evanhevanh Posts: 15,916
    edited 2019-05-18 16:14
    I've had the core up to about 2 Amps on its switcher I believe. I had to pre-cool it with ice packs ... and, due to the extreme clock rate, it didn't last long before crashing. I had all 8 cogs feeding the cordic and doing MULs. Wasn't doing any hubRAM work though.
  • cgraceycgracey Posts: 14,153
    edited 2019-05-18 19:05
    Peter Jakacki wrote: »
    So the 2A switcher I have on my P2D2 is way under-rated then? :) But so is the copper.

    Because of this I may stress test a P2 chip if I'm game, at least up to 2A. Isn't there a problem with too much current flowing through the substrate and the resultant voltage drop/rise?

    Silicon substrate currents are near zero. The metal layers move all the current and the output FETs will exhibit the most drop.
  • RaymanRayman Posts: 14,646
    Can all P2 pins source or sink 30 mA at the same time?
    That would be great.

    I think P1 is 40 mA per pin and 300 mA total. So, only a few pins can be drawing max current...
  • cgraceycgracey Posts: 14,153
    Rayman wrote: »
    Can all P2 pins source or sink 30 mA at the same time?
    That would be great.

    I think P1 is 40 mA per pin and 300 mA total. So, only a few pins can be drawing max current...

    I think it all comes down to acceptable heat contribution, not design limits of pins.
  • TubularTubular Posts: 4,702
    There are 16 VIo pins on P2, vs the 4 on P1, but the P2 pins are local to 4 IO, so there will be no trouble

    At around 20 ohm switch impedance thats around 165mA into a short circuit, or 80 mA into a matched impedance load

    When doing DAC testing, there was a few millivolts difference between outputting a digital strong low, to analog dac level 0, that I think reveals the impedance of the gold wires and bus on the pin pads.
  • evanhevanh Posts: 15,916
    edited 2019-05-19 02:13
    Just tried it out: Placing a 100.26 ohm resistor from GND to an output and it sourced to 2.78 volts. VIO measured at 3.308, which comes to 19.04 ohms sourcing.
    A 99.6 ohm resistor from VIO to an output and it sinked to 0.468 (-2.838) volts. VIO = 3.306 which comes to 16.42 ohms sinking.

    Those were single separate pin tests.
  • hinvhinv Posts: 1,255
    cgracey wrote: »
    evanh wrote: »
    I'm counting the core too. Lol, I wasn't being serious.

    Yes, the core power connections would make it 32 Amps. We won't have a wiring problem.

    Wow! Is there ANY other microcontroler that will do anything close?
  • evanhevanh Posts: 15,916
    Ah, no, but Parallax won't be saying anything like that in the official datasheet. Chip has suggested max of 30 mA per output. Experimenting says that's already a decent load. More and heat generation will climb fast.
  • jmgjmg Posts: 15,173
    evanh wrote: »
    .... Chip has suggested max of 30 mA per output. Experimenting says that's already a decent load. More and heat generation will climb fast.
    ..
    A 99.6 ohm resistor from VIO to an output and it sinked to 0.468 (-2.838) volts. VIO = 3.306 which comes to 16.42 ohms sinking.

    Yes, taking 60 pins at that 28.5mA, is ~800mW of added power load, which is quite significant.
    MOSFET Rds is also positive tempco, so is prone to thermal runaway, needing more care with cooling.

    Running all the DACs is likely to be a challenge thermally too.
  • TubularTubular Posts: 4,702
    19 ohms is what I remember, too. I think the results I took are buried in a thread somewhere here. It'll vary a bit under load and depending on supply voltage, but its a good strong useful output that will probably drive things like high sensitivity relay coils just fine. I know Ozprop and I had it hooked up directly driving a bookshelf speaker with satisfying results in the early days, though we stopped doing that when we remembered there weren't many chips out there yet (and really musn't damage one so early).

    Chip mentioned before I think the sourcing and sinking impedances should be close near midrange.

    I think the 30mA figure Chip gave is probably *really* conservative [img][/img]
  • MJBMJB Posts: 1,235
    edited 2019-05-19 10:46
    jmg wrote: »
    MOSFET Rds is also positive tempco, so is prone to thermal runaway, needing more care

    With P = U*U/R

    Rising R should not run away ?
  • samuellsamuell Posts: 554
    MJB wrote: »
    MOSFET Rds is also positive tempco, so is prone to thermal runaway, needing more care

    With P = U*U/R

    Rising R should not run away ?
    Mind that the MOSFET is in series with the load. If Rds increases, the voltage drop (Vds) across it will also increase. Assuming that the load current stays roughly the same (the influence of Vds/Rds is negligible on the load), you can define Pmos as a function of I and Rds (U is not constant, and is a function of R for the reason above):

    Pmos = I² * Rds

    So, if R increases, the dissipated power across the MOSFET, P, also increases.

    Kind regards, Samuel Lourenço
  • MJBMJB Posts: 1,235
    jmg wrote: »
    evanh wrote: »
    .... Chip has suggested max of 30 mA per output. Experimenting says that's already a decent load. More and heat generation will climb fast.
    ..
    A 99.6 ohm resistor from VIO to an output and it sinked to 0.468 (-2.838) volts. VIO = 3.306 which comes to 16.42 ohms sinking.

    Yes, taking 60 pins at that 28.5mA, is ~800mW of added power load, which is quite significant.
    MOSFET Rds is also positive tempco, so is prone to thermal runaway, needing more care with cooling.

    Running all the DACs is likely to be a challenge thermally too.
    samuell wrote: »
    MJB wrote: »
    MOSFET Rds is also positive tempco, so is prone to thermal runaway, needing more care

    With P = U*U/R

    Rising R should not run away ?
    Mind that the MOSFET is in series with the load. If Rds increases, the voltage drop (Vds) across it will also increase. Assuming that the load current stays roughly the same (the influence of Vds/Rds is negligible on the load), you can define Pmos as a function of I and Rds (U is not constant, and is a function of R for the reason above):

    Pmos = I² * Rds

    So, if R increases, the dissipated power across the MOSFET, P, also increases.

    Kind regards, Samuel Lourenço

    Thanks
    Makes sense
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