10MB washing machine sized HDDs were $16,000 ea in 1976 when they were discontinued. Field Engineers who repaired the minicomputers and mainframes of the day were paid about $6,500 pa.
"Do you think we connected it up right?"..... "Dunno, switch on and let's find out"
:-D
Have a look at the P2D2, it is barely 50% wider than the DIP version and only a fraction longer but then again it does have USB serial built-in as well as the regulators and memory etc. Sure, the P2 is overkill if you can do it with a P1, but it is also a lot easier to do it with the P2 and a lot more powerful and flexible and fun.
If you think a P2 is overkill look at what they are doing with RPIs, and they have a lot of projects that I'm sure could be done with a P1 yet they devote 1GB RAM + 64-bit Quad core ARMs to the task.
10MB washing machine sized HDDs were $16,000 ea in 1976 when they were discontinued. Field Engineers who repaired the minicomputers and mainframes of the day were paid about $6,500 pa.
"Do you think we connected it up right?"..... "Dunno, switch on and let's find out"
:-D
I used to teach maintenance on those HDDs. My students had to break a drive(s) into components and then rebuild it/them. And they were brand new HDDs. Luckily I never lost any drives
[soap box]
I am eager to start using the P2, but I am a busy person and I can't deal with the constant changes being made.
Once the design and commands are "set in stone" then I will get involved.
From the brief understanding I have of the P2 it appears to be a true quantum leap from the P1, but I would have been happy with a P1 with 64 I/O and more RAM.
It's a shame that the P2 is only 8 cogs. I was really hoping for a 16 cog P2.
I once commented that the P2 would be "The greatest microcontroller never made." I hope I was wrong about that, but that was several years ago...
[/soap box]
Bean
I didn’t need/use a heat sink on the P2 ES chip.
There was a time where we thought it might be required until we understood the chip better. Of course if you push it too the limits then that may be a different story, but i doubt many will.
While we only ended up with 8 cogs, we have streamers, smartpins, and 512KB of Hub Ram, and 4KB per cog too. And hubexec with the eggbeater. Lots of horsepower there if you need it.
The P2 will be totally amazing. What is more amazing is the ten year wait. Much of this played out in continued robust public debating. Whilst this has been going on seems most of the forum supporters saw the open door and walked through it. I wanted a propeller board and thought about Spinvent - he has packed up. I think Parallax is more about education and modules and not so much about becoming a chip supplier. Sure Ken will chime in with some marketing information. I find myself curious what the spend has actually been to this point, you would know the answer to this question.
Too many choices in processor land now, a one-man design team might be a good model and fit for own purpose. Strange that bigger players do not do the same? I suspect is not common as they know will hit the same type of car crashes.
Yeah I really wanted that Spinvent board, he was advertising it, way after it was even available. I ended up buying all of his remaining stock.
Lot of emphasis on robotics today and my field of expertise is industrial robotics, CNC and automation. The P2 is, potentially, the dream processor for these applications.
Show me a GP microcontroller that can handle more than two quadrature encoders... Dedicated *single* axis motion processors start at $30.
Industry standard robots and machine tools don't use open-loop stepper motors.
Size and power requirements? Show me what you would use for a six axis robot controller with encoder feedback...The P2 could handle this without breaking a sweat.
I am only able to do some light P1 work at the moment, because life.
Re: power
Remember the clock. This chip is useful at 40Mhz and up, depending on what you need to do.
The way I see it, we have pretty great tools right now. I have had a few go arounds and am excited about progress. Self hosting options already! (I did not expect Micropython, and with RISC V emulation!)
Being able to run PASM in the HUB makes a lot of things easier and or closer, if one wants it, to more traditional ways of working, though the real potential is still the Propeller way.
I have a product, maybe two in mind.
Re: the wait and robust public debate
I feel very strongly this is a strength. Our current eval boards are very useful. So much got done right. It is crazy.
[soap box]
I am eager to start using the P2, but I am a busy person and I can't deal with the constant changes being made.
Once the design and commands are "set in stone" then I will get involved.
From the brief understanding I have of the P2 it appears to be a true quantum leap from the P1, but I would have been happy with a P1 with 64 I/O and more RAM.
It's a shame that the P2 is only 8 cogs. I was really hoping for a 16 cog P2.
I once commented that the P2 would be "The greatest microcontroller never made." I hope I was wrong about that, but that was several years ago...
[/soap box]
P2 is already made, so hopefully, that bit is already proven wrong
The design and commands are "set in silicon" - is that close enough for you ? Software development looks to be going at great speed,
The DOCs need some work, and the final exact MHz specs will be worked based on silicon tests.. fingers crossed it's all 'better' on the new (final?) spin ?
P2 COGS are more powerful than P1 COGS, and they are all the same full-spec COGS, plus there are events/interrupts.
16 COGs was too much die space, and Chip did not want to make cogs asymmetric,
The problem I have with cost here is that to run the P2 you need twice as much space as the chip just to power it and cool it. It's not just buy the chip for $8.00 and your done.
Yes, P2 has dual power supplies, but `twice as much space as the chip just to power it and cool it` is somewhat flexible.
The first P2-EV board uses quite old SMPS tech, and conservative too, as well as conservative cooling. So yes, it is 'big'.
I believe the SMPS has updates on the next P2-EV
That's certainly the right approach for first boards, you need 'best cooling' and 'best power', in order to be testing what the silicon can do.
Final customer boards can be more tuned to needs, and the power supply choices are expanding.
The pivotal moment could be to see what PAL video signal this can push out. The UK PAL quality from Propeller 1 was a reasonable car crash. HDMI should be better without needing to play with standards. I understand that people love to debate matters until everyone goes totally mad or just gives up.
The UK PAL quality from Propeller 1 was a reasonable car crash.
What, you don't love diagonal lines moving through your image? smh.
(Altough the PAL60 timings I came up with don't suffer from this nearly as much. Sad that only seems to have been discovered in 2018)
AFAICT P2 shouldn't suffer from the same problem as it doesn't use a secondary PLL driven by a jittery NCO to generate the color carrier (instead, a phase accumulator running off the main clock is used). Just the sheer higher clock frequency helps, too.
I have a product that I'm bringing to market this year. It is designed around the Prop1 and a PIC18F processor. If the Prop2 were in production, I'd be able to do the design with just the Prop2. Actually most of the app is running on the PIC18F because it has 128K or FLASH for the code and 8K of RAM for the screen and other things. When the Prop2 comes out, I'll be able to have it do ALL the app and it will way more powerful.
What I'm doing can only be done with a Prop1 / Prop2 type processor.
Looking forward very much to the Prop2 going into production later this year. I think it will make Rev 2 of my product much easier to write and will take it to the next level.
What function is the PIC18F handling and is the reason because of hardware or software or memory limitations of the P1? It's just that I have been able to cram a mighty lot into the humble P1 with Tachyon.
Sorry for the late reply.
I'm using the PIC 18F as a graphics driver for a 128x64 OLED display and also to read several analog channels. It's kinda funny as initially the P1 was going to handle everything, but because it doesn't do analog directly, I needed an analog chip. And it just didn't make since to use a dedicated analog chip at like $4-$5 when I can get the PIC18F27K42 for like $2. It has more analog channels and 8K RAM & 128KB flash. More and more I thought about it, the PIC became the main application chip and the P1 became the fast IO Chip. I was quite worried that I'd run out of application space with the P1 only having 32K total memory. I'm using a FLiP so I will also use the P1 do do all the reflashing tasks for both chips. I need a design that will not allow an SD card slot. Just a USB connector.
I do plan on a total redesign once the P2 is fully released, but for now I have a design that I think I can work with. The P2 will probably be the only processor on the 2nd revision of the product. With 512K of memory and the ability to pull on other memory assets easy on the P2 will make it much easier.
.... And it just didn't make since to use a dedicated analog chip at like $4-$5 when I can get the PIC18F27K42 for like $2. It has more analog channels and 8K RAM & 128KB flash....
Yes, these days modest priced MCUs are taking on the 10/12/14b ADC's and 12b DAC's
Parts like EFM8BB3 with 12 channels of 12b SAR ADC, and 2 channels of 12b DAC, are 64c/3k
Yes, I've used those little 8-pin PICs such as the 12F1572 as smart A/D where they just continually send back analog data over serial over isolated links so all it needs is one I/O on the Prop to read whenever it wants. The other thing is that these cheap micros also have voltage reference (plus the kitchen sink) which many dedicated A/D chips don't. Why would you use the MCP320x for instance and they aren't cheap?
But surely the graphics driver could have been done directly in the Prop much easier.
That doesn't make sense. The PIC is 61 cents and the MCP3202 is $2.61 and there made by the same company. You would think they made there money on those devices already and would charge the same amount for them.
I guess the demand for one is not the same as the other?
But surely the graphics driver could have been done directly in the Prop much easier.
No doubt. But I already had much of the graphics driver on the PIC already written from prior projects. The biggest issue was not having enough code space on the Prop. The prop is so much easier to code in and get a ton done. Having to deal with interrupts on the PIC is a PITA. Such that to make quick work of the key/switch interface, I have the Prop doing that in a free cog and sending it he PIC in the serial connection between the two.
Overall, it's a nice setup using each processor where it shines. For the fast I/O that I need to ensure I catch EVERY transition, the Prop is the only real processor that will do that as easy as it does.
@JimFouch2 - while I understand using the PIC for analog it's also a pity that you (and so many others) ran out of memory on the Prop when really the Prop has enough memory. The problem is with the software and libraries and methods. In Tachyon my SSD2119 SPI driver which could draw Prop or 5x7 fonts to the QVGA color screen as well as graphics only required a few hundred bytes. Indeed, even the primary conduit to the screen was a simple one-liner function called LCD! that took 26 bytes and probably around 10us, but even that could have been optimized if I had been bothered.
pub LCDDAT ( pixels -- ) $22
--- write cmd and data to display SPI bus
pub LCD! ( data reg -- ) SPIWR DROP DUP 8<< $100 OR SPIWR DROP $100 OR SPIWR DROP ;
I've been away for a while while the P2 was being developed, but it seems to me that the jump between the P1 to the P2 is similar to going from a Vic20 to an Amiga. Reading the "UNOFFICIAL Preliminary Short Term Data", it seems a lot of capability packed into those pins. I can't wait to get the Propeller2 Manual and P2 Demo Board when Parallax get's them done. Learning from the P1 version of those was quite fun.
That said, I can still see a fit for a P1B with the following upgrades:
Working MUL and DIV instructins 16x16 or 32/16 in 4 cycles
Simple DESerializer handled in the counters.
64KB hub RAM, only 2KB ROM that is copied to hub RAM after/during power up.
64 IO, of course
P1 code compatibility, same voltage requirements, 40pin P1 compatible package as a drop in upgrade.
That said, I can still see a fit for a P1B with the following upgrades:
Working MUL and DIV instructins 16x16 or 32/16 in 4 cycles
Simple DESerializer handled in the counters.
64KB hub RAM, only 2KB ROM that is copied to hub RAM after/during power up.
64 IO, of course
P1 code compatibility, same voltage requirements, 40pin P1 compatible package as a drop in upgrade.
That would be a lot of new product development work, but Chip has designed the P2 verilog code to be scalable, so there could be other P2 variants, subject to enough big-customer demand.
It may be possible to have a BGA package version of P2, which would shrink the package size significantly.
You can fit a TQFP100 P2 on a DIP40 module now, with around 0.9" to 0.95" size, and a BGA would allow that overhang to reduce.
The P2 smartpins for me are mostly a distraction. the 32-bit wide WRPIN would take a book in itself to explain properly. The %TT bits are a nightmare to understand. Why is Mode shifted left by one bit? Why doesn't the list of modes just include the LSB zero? 6 bits instead of 5 -- All I'm saying is the documentation has a long long way to go.
The high cpu clock speed, DRVH style pin instructions, and multiplication instructions are much appreciated.
The P2 chip isn't that large. Why is there demand for an exact drop-in DIP socket format?
Breadboards can take a wider space between rows than 0.600"
One can totally make a FLiP like board that would be 0.800" for example.
And one can just ignore most of the extra added stuff and run compiled code like you've always been doing.
In other words, I highly doubt there's this untapped market of DIP-40 sockets just waiting to have their P1 switched out. I think if anything the P1 DIP is just being plugged into breadboards.
Comments
:-D
If you think a P2 is overkill look at what they are doing with RPIs, and they have a lot of projects that I'm sure could be done with a P1 yet they devote 1GB RAM + 64-bit Quad core ARMs to the task.
I used to teach maintenance on those HDDs. My students had to break a drive(s) into components and then rebuild it/them. And they were brand new HDDs. Luckily I never lost any drives
There was a time where we thought it might be required until we understood the chip better. Of course if you push it too the limits then that may be a different story, but i doubt many will.
While we only ended up with 8 cogs, we have streamers, smartpins, and 512KB of Hub Ram, and 4KB per cog too. And hubexec with the eggbeater. Lots of horsepower there if you need it.
Too many choices in processor land now, a one-man design team might be a good model and fit for own purpose. Strange that bigger players do not do the same? I suspect is not common as they know will hit the same type of car crashes.
Lot of emphasis on robotics today and my field of expertise is industrial robotics, CNC and automation. The P2 is, potentially, the dream processor for these applications.
Show me a GP microcontroller that can handle more than two quadrature encoders... Dedicated *single* axis motion processors start at $30.
Industry standard robots and machine tools don't use open-loop stepper motors.
Size and power requirements? Show me what you would use for a six axis robot controller with encoder feedback...The P2 could handle this without breaking a sweat.
Will it likely be able to fit the same footprint so we can plop it on top of ActivityBots?
I am only able to do some light P1 work at the moment, because life.
Re: power
Remember the clock. This chip is useful at 40Mhz and up, depending on what you need to do.
The way I see it, we have pretty great tools right now. I have had a few go arounds and am excited about progress. Self hosting options already! (I did not expect Micropython, and with RISC V emulation!)
Being able to run PASM in the HUB makes a lot of things easier and or closer, if one wants it, to more traditional ways of working, though the real potential is still the Propeller way.
I have a product, maybe two in mind.
Re: the wait and robust public debate
I feel very strongly this is a strength. Our current eval boards are very useful. So much got done right. It is crazy.
The design and commands are "set in silicon" - is that close enough for you ? Software development looks to be going at great speed,
The DOCs need some work, and the final exact MHz specs will be worked based on silicon tests.. fingers crossed it's all 'better' on the new (final?) spin ?
P2 COGS are more powerful than P1 COGS, and they are all the same full-spec COGS, plus there are events/interrupts.
16 COGs was too much die space, and Chip did not want to make cogs asymmetric,
The first P2-EV board uses quite old SMPS tech, and conservative too, as well as conservative cooling. So yes, it is 'big'.
I believe the SMPS has updates on the next P2-EV
That's certainly the right approach for first boards, you need 'best cooling' and 'best power', in order to be testing what the silicon can do.
Final customer boards can be more tuned to needs, and the power supply choices are expanding.
Sue.
What, you don't love diagonal lines moving through your image? smh.
(Altough the PAL60 timings I came up with don't suffer from this nearly as much. Sad that only seems to have been discovered in 2018)
AFAICT P2 shouldn't suffer from the same problem as it doesn't use a secondary PLL driven by a jittery NCO to generate the color carrier (instead, a phase accumulator running off the main clock is used). Just the sheer higher clock frequency helps, too.
Sorry for the late reply.
I'm using the PIC 18F as a graphics driver for a 128x64 OLED display and also to read several analog channels. It's kinda funny as initially the P1 was going to handle everything, but because it doesn't do analog directly, I needed an analog chip. And it just didn't make since to use a dedicated analog chip at like $4-$5 when I can get the PIC18F27K42 for like $2. It has more analog channels and 8K RAM & 128KB flash. More and more I thought about it, the PIC became the main application chip and the P1 became the fast IO Chip. I was quite worried that I'd run out of application space with the P1 only having 32K total memory. I'm using a FLiP so I will also use the P1 do do all the reflashing tasks for both chips. I need a design that will not allow an SD card slot. Just a USB connector.
I do plan on a total redesign once the P2 is fully released, but for now I have a design that I think I can work with. The P2 will probably be the only processor on the 2nd revision of the product. With 512K of memory and the ability to pull on other memory assets easy on the P2 will make it much easier.
Parts like EFM8BB3 with 12 channels of 12b SAR ADC, and 2 channels of 12b DAC, are 64c/3k
But surely the graphics driver could have been done directly in the Prop much easier.
I guess the demand for one is not the same as the other?
Mike
Also, perhaps the analog adcs use a costlier process than the mcus.
Either way, unless the adc has something special that the mcu doesnt, why wouldnt you use the mcu? Which only compounds the cost issue.
-Phil
No doubt. But I already had much of the graphics driver on the PIC already written from prior projects. The biggest issue was not having enough code space on the Prop. The prop is so much easier to code in and get a ton done. Having to deal with interrupts on the PIC is a PITA. Such that to make quick work of the key/switch interface, I have the Prop doing that in a free cog and sending it he PIC in the serial connection between the two.
Overall, it's a nice setup using each processor where it shines. For the fast I/O that I need to ensure I catch EVERY transition, the Prop is the only real processor that will do that as easy as it does.
That said, I can still see a fit for a P1B with the following upgrades:
Working MUL and DIV instructins 16x16 or 32/16 in 4 cycles
Simple DESerializer handled in the counters.
64KB hub RAM, only 2KB ROM that is copied to hub RAM after/during power up.
64 IO, of course
P1 code compatibility, same voltage requirements, 40pin P1 compatible package as a drop in upgrade.
That would be a lot of new product development work, but Chip has designed the P2 verilog code to be scalable, so there could be other P2 variants, subject to enough big-customer demand.
It may be possible to have a BGA package version of P2, which would shrink the package size significantly.
You can fit a TQFP100 P2 on a DIP40 module now, with around 0.9" to 0.95" size, and a BGA would allow that overhang to reduce.
Parallax may decide to do a FLiP-P2 for example?
The high cpu clock speed, DRVH style pin instructions, and multiplication instructions are much appreciated.
The P2 chip isn't that large. Why is there demand for an exact drop-in DIP socket format?
Breadboards can take a wider space between rows than 0.600"
One can totally make a FLiP like board that would be 0.800" for example.
And one can just ignore most of the extra added stuff and run compiled code like you've always been doing.
In other words, I highly doubt there's this untapped market of DIP-40 sockets just waiting to have their P1 switched out. I think if anything the P1 DIP is just being plugged into breadboards.