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Can I Place Things Underneath A P1? — Parallax Forums

Can I Place Things Underneath A P1?

I am building a modular Propeller-based computer, and I am getting my first experience routing a q-44(qfp) chip. I’m order to keep from interfering with the IO traces, I would like to lay traces from the power pins to the inside and then jump them out on another layer with vias. Can I do this?

Comments

  • AwesomeCronkAwesomeCronk Posts: 1,055
    edited 2019-03-23 16:30
    I would like to put vias right about where "U1" is.
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  • You could as long as you keep the bypass caps close to the chip. Two layer or four?
  • Only using two at the time. What are bypass caps? Using the schematic on pg 17 of the Propeller manual to build this circuit.
  • In the following PDF you will see 4-caps, C1-C4 that span VSS and VDD.

    https://www.parallax.com/sites/default/files/downloads/40000-Propeller-QuickStart-Schematic-Layout-RevB.pdf

    Bypass caps are also refered to as a decoupling cap:

    https://en.wikipedia.org/wiki/Decoupling_capacitor

    Four caps are needed on the QFP. Leaving them out leads to failure of the PLL.
  • Thank you. I would have toasted all of my p1s on the boards and not been able to understand why the timing was gone.
  • Peter JakackiPeter Jakacki Posts: 10,193
    edited 2019-03-23 23:49
    To all who would like some practical tips in regards to laying out a pcb.

    All things are relative and when it comes to bypass caps it depends upon type, value, placement, effective impedance, load, frequency etc. I have hardly ever used 4 caps myself but I have seen 4 caps used ineffectively even when they have been placed close to the chip because of the long circuitous path the caps are connected with.

    Having a fairly solid ground and power plane helps and I have only ever used two sided pcbs so it is possible.
    Using a lower value cap rather a "bigger and better'er" one helps.
    Having a small regulator closer to the chip helps rather than a TO220 monster. (they mostly only need less than a 100ma).
    There are plenty of factors and if you are not sure then use 4 or more caps but then they really really need to be physically and electrically as close to the pins as possible.

    Of course all this goes out the window when those HC49 monster crystals are used and then not placed as close as possible since the crystal input pin is like a sensitive antenna ready to pick up noise that affects the clock that affects every aspect of the chip etc.

    The other aspect of P1 pcb layout that needs to be considered is the ground current path so be careful of heavy ground currents that could pass through the CPU when you are driving motors etc. Always best to have the power ground and the load ground taken from the same point. Most P1s (the internal PLL) have been destroyed because of not observing this simple detail.

    Here's a sample of a P1 I did several years ago using just 2 caps (the 104s) plus one bulk cap (475) a little further away. In other designs I have even had just one cap without problems, but then again this depends upon the design and use.

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  • Peter,

    When you say the power ground and the load ground should come from the same place, is that what Dave Jones of EEVBlog calls a "star point"?
  • Peter JakackiPeter Jakacki Posts: 10,193
    edited 2019-03-24 00:38
    Genetix wrote: »
    Peter,

    When you say the power ground and the load ground should come from the same place, is that what Dave Jones of EEVBlog calls a "star point"?

    I guess you could call it that in that but the main thing I do is visualize the current flows and resultant voltage drops (static and dynamic) and if you imagine a 3A load then you would visualize the current flowing from the battery or supply to that point and then back "out" to the load nice and cleanly with the "ground" reference also used by logic not changing. So it doesn't flow through the ground plane of a board with a resultant voltage difference which would also affect logic thresholds and of course introduce load noise into the control section where you have all those mysterious lockups and damaged chips etc.

    Poor bypass cap placement is perhaps exemplified when plug-in breadboards are used that have long wires going to grounds and then caps with long leads uncut pushed into some ground and power somewhere on the board but electrically on "the other side of town". Keep these connections as short and as close as possible and sometimes that is right on the pins themselves. Every bit of wire or track has some resistance and inductance that add up especially at high frequencies and currents. (That is why some test circuits seem to work but fail when shifted into high gear).
  • For high speed decoupling the stray inductance is what matters, the resistance is not going to be an issue
    when the inductive reactance is measured in 100's and 1000's of ohms at the frequencies of interest.

    This why power traces should be wide, to reduce inductance between chip and decoupling cap, and why
    they should run over a groundplane. Its also why its common to see multiple decoupling caps, a small one
    right at the pin, a larger one behind it - the lead length (and thus inductance) between chip pin and first
    decoupling cap is crucial for the high speed decoupling to be effective.
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