Eg: The long tracks on the board for the uSD and flash chip are slowing down the upper few pins even more than the rest. At 350 MHz needs w=6 for those few.
That loading effect is quite brutal, I wonder if the next Eval can fix that, with better placement and routing ?
An aside: There is notable extra current draw with I/O clocking. Here's a table for my 5 volt bench supply:
Is that for IO Clocking enabled on every pin ?
Surprising, really, as the clock tree has to be always feeding into the pins, and Enable has to merely flip a MUX to D-F or direct, and the edge rates in both should be identical, and fairly low ?
I wonder whether its something to do with having to go through 1v8 (core) to 3v3 (pad) level translators
I'm sure level shifting has a delay-adder, plus as things get larger and more robust, they get slower...
Chip has mentioned the ESD elements come at a cost too...
Every extra 20pF with ~ 30mA of peak drive, should add about 1ns ?
60 registered pins. It would have been 62 but pins 8 and 9 are reused for the sync.serial testing.
Both runs leave those 60 pins enabled and high upon completion. Oh, and powered from the LDO's.
Hmm, the 3v3 switcher is a little worse! *shrug* Bah! I'm using the adjustable supply at the moment. The 5 volts won't be the same this time. It looking the same with either LDO or switcher.
888 mA is a constant on the 1v8 rail when at 300 MHz. Doesn't make any diff what I do with the I/O config. So all the diff is in the 3v3 rail.
Hmm. maybe the D-F is in the IO voltage domain, and so both a MUX and a level-shifter are enabled to change, for each pin case.
That level shifter and now active load may account for the almost 1mA/pin added ?
The capacitive part of clocking power loss in CMOS is simple to calculate, its f.C.V^2, f being frequency, C being capacitance,
f being clock frequency - for a 3.3V signal at 350MHz that comes to about 4mW/pF (ie > 1mA/pF). This loss is due
to resistance losses in the switching elements when charging/discharging the stray capacitances, but the formula is
independent of the resistance itself.
The other loss is shoot-through conduction losses, which are proportional to frequency (and also depends on
temperature and voltage as these determine switching speed, and voltage determines conduction overlap region
of each stage)
This is why you see really high speed logic signals sent around PCBs as LVDS pairs routed on the surface layers.
Low voltage reduces losses, using transmission line prevents the total line capacitance from affecting the loss
so the signal paths can be much longer (the depedence of the loss formula on frequency is eliminated)
This is why you see really high speed logic signals sent around PCBs as LVDS pairs routed on the surface layers.
Low voltage reduces losses, using transmission line prevents the total line capacitance from affecting the loss
so the signal paths can be much longer (the depedence of the loss formula on frequency is eliminated)
I can see why this didn't occur with the P2ES EVAL board. To make room for I/O tracks to remain on the top of the PCB would need moving of the capacitors and it would be difficult to keep the power jumpers.
Maybe both could move near the corners of the chip. Or for the caps, spread them enough to allow two tracks between each would do it. And that keeps them in pairs too.
I'd be loth to have anything protruding off the bottom of the PCB. The bottom is nicely arranged for passive heat sinking.
Caps often go on the underside to avoid cluttering signal routing, with BGA packages its a necessity.
Of course there's plus and minus to everything - top routed signals spray more EMI around, another
motivation for LVDS.
The evaluation board spreads the heat really well so the whole board acts as a heatsink, but in a smaller
PCB that's clearly less effective.
Perhaps bottom side caps can be thought of as very small thermal cooling fins?
I've been measuring the 3v3 switcher current with all VIO jumpered. One thing that I came across is the static current increases when all DIRs are low vs high. I'm thinking this will be floating input levels imparting active currents in the input buffers.
The increase is temperature dependent. Maybe 0.5 mA at 10oC to a tiny 0.01 mA up at 50oC.
Interesting there is a slight slope, even on no clocked.
I make the CPD model equivalent for those columns 5pF and 53pF
The 5pF is always there, so there is no per-pin choice.
The 53pf is ~ 0.87pF/Active Clocked Pin.
Comments
That loading effect is quite brutal, I wonder if the next Eval can fix that, with better placement and routing ?
Is that for IO Clocking enabled on every pin ?
Surprising, really, as the clock tree has to be always feeding into the pins, and Enable has to merely flip a MUX to D-F or direct, and the edge rates in both should be identical, and fairly low ?
I'm sure level shifting has a delay-adder, plus as things get larger and more robust, they get slower...
Chip has mentioned the ESD elements come at a cost too...
Every extra 20pF with ~ 30mA of peak drive, should add about 1ns ?
60 registered pins. It would have been 62 but pins 8 and 9 are reused for the sync.serial testing.
Both runs leave those 60 pins enabled and high upon completion. Oh, and powered from the LDO's.
Hmm, the 3v3 switcher is a little worse! *shrug* Bah! I'm using the adjustable supply at the moment. The 5 volts won't be the same this time. It looking the same with either LDO or switcher.
Hmm. maybe the D-F is in the IO voltage domain, and so both a MUX and a level-shifter are enabled to change, for each pin case.
That level shifter and now active load may account for the almost 1mA/pin added ?
f being clock frequency - for a 3.3V signal at 350MHz that comes to about 4mW/pF (ie > 1mA/pF). This loss is due
to resistance losses in the switching elements when charging/discharging the stray capacitances, but the formula is
independent of the resistance itself.
The other loss is shoot-through conduction losses, which are proportional to frequency (and also depends on
temperature and voltage as these determine switching speed, and voltage determines conduction overlap region
of each stage)
This is why you see really high speed logic signals sent around PCBs as LVDS pairs routed on the surface layers.
Low voltage reduces losses, using transmission line prevents the total line capacitance from affecting the loss
so the signal paths can be much longer (the depedence of the loss formula on frequency is eliminated)
I can see why this didn't occur with the P2ES EVAL board. To make room for I/O tracks to remain on the top of the PCB would need moving of the capacitors and it would be difficult to keep the power jumpers.
Maybe both could move near the corners of the chip. Or for the caps, spread them enough to allow two tracks between each would do it. And that keeps them in pairs too.
I'd be loth to have anything protruding off the bottom of the PCB. The bottom is nicely arranged for passive heat sinking.
Of course there's plus and minus to everything - top routed signals spray more EMI around, another
motivation for LVDS.
The evaluation board spreads the heat really well so the whole board acts as a heatsink, but in a smaller
PCB that's clearly less effective.
Perhaps bottom side caps can be thought of as very small thermal cooling fins?
The increase is temperature dependent. Maybe 0.5 mA at 10oC to a tiny 0.01 mA up at 50oC.
3v3 VIO supply current (Prop2 quiescent) UnClkd Clocked MHz | mA mA =====|============== 10 | 1.0 2.6 50 | 1.5 9.6 100 | 2.2 18.4 150 | 2.95 27.0 200 | 3.7 35.7 250 | 4.4 44.2 300 | 5.1 52.6 350 | 5.8 60.9Interesting there is a slight slope, even on no clocked.
I make the CPD model equivalent for those columns 5pF and 53pF
The 5pF is always there, so there is no per-pin choice.
The 53pf is ~ 0.87pF/Active Clocked Pin.