Reading the state of a smartpin

Peter Jakacki

While looking at helping @FredBlais with a simple bitbanged I2S I thought of outputting a constant clock for the BCLK and then shifting out each data bit by synchronizing to the clock edge. Trouble is I can't recall correctly how we should do that?

For the last attempt I gave up and I've have just used a wait to time the data but of course it is not synchronized with the clock.

48 := BCLK
49 := DIN
CLKHZ 16000 U/ := TR
BCLK PIN 16 KHZ
: I2S ( data16 --- )
	15 << DIN 
	TR WAITX
	17 FOR WAITCNT MSBOUT NEXT
	2DROP
	;

MSBOUT shifts the msb of the data out to the specified pin while updating the data but leaving the stack intact ( data pin -- data<<1 pin )

jmg

Peter Jakacki wrote: »

While looking at helping @FredBlais with a simple bitbanged I2S I thought of outputting a constant clock for the BCLK and then shifting out each data bit by synchronizing to the clock edge. Trouble is I can't recall correctly how we should do that?

IIRC that's done using this mode ?
11100* = sync serial transmit (A-data, B-clock)

Words of 1 to 32 bits are shifted out on the pin, LSB first, with each new bit being output two internal clock cycles after registering a positive edge on the B input. For negative-edge clocking, the B input may be inverted by setting B[3] in WRPIN’s D value.

Peter Jakacki

jmg wrote: »

Peter Jakacki wrote: »

While looking at helping @FredBlais with a simple bitbanged I2S I thought of outputting a constant clock for the BCLK and then shifting out each data bit by synchronizing to the clock edge. Trouble is I can't recall correctly how we should do that?

IIRC that's done using this mode ?
11100* = sync serial transmit (A-data, B-clock)

Words of 1 to 32 bits are shifted out on the pin, LSB first, with each new bit being output two internal clock cycles after registering a positive edge on the B input. For negative-edge clocking, the B input may be inverted by setting B[3] in WRPIN’s D value.

While I could use the smart pin modes, this was more of a learning exercise at the bit-bashing level. Certainly in a real application we would make use of this mode.

So the question remains nonetheless, how do we read the state of a pin that is configured as a smart pin?

Tubular

OzProp was using a neighboring pin to spy, I believe

ozpropdev

Use a pin nearby (+/-3 pins) and redirect its input using smart pin mode %00000.

D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0

%AAAA: ‘A’ input selector
0xxx = true (default)
1xxx = inverted
x000 = this pin’s read state (default)
x001 = relative +1 pin’s read state
x010 = relative +2 pin’s read state
x011 = relative +3 pin’s read state
x100 = this pin’s OUT bit from cogs
x101 = relative -3 pin’s read state
x110 = relative -2 pin’s read state
x111 = relative -1 pin’s read state

Peter Jakacki

ozpropdev wrote: »

Use a pin nearby (+/-3 pins) and redirect its input using smart pin mode %00000.

D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0

%AAAA: ‘A’ input selector
0xxx = true (default)
1xxx = inverted
x000 = this pin’s read state (default)
x001 = relative +1 pin’s read state
x010 = relative +2 pin’s read state
x011 = relative +3 pin’s read state
x100 = this pin’s OUT bit from cogs
x101 = relative -3 pin’s read state
x110 = relative -2 pin’s read state
x111 = relative -1 pin’s read state

Thanks, I was wondering if I "needed" to do that. Sure seems an awkward way just to read the pin directly. Oh well

ozpropdev

Peter Jakacki wrote: »

Sure seems an awkward way just to read the pin directly. Oh well

I found in testing I had to plan the position of my smart pins so I could "reach" their output states with other "snoop" pins.
It was the only way I could capture all the signals I needed with the streamer (P2 logic analyzer)