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P2-Eval LDO Oscillation - No CL — Parallax Forums

P2-Eval LDO Oscillation - No CL

jmgjmg Posts: 15,173
in Propeller 2
As I feared, the no CL PCB layout has the LDOs not stable.
This means you should not connect external circuits to the 3v3 labeled pins, without adding a large enough decoupling cap.
When the jumper moves on the PCB, the fitted cap is then connected to the LDO, so it should be ok.

Scope captures show the oscillation at no load, and at 40mA ( At 2mA it is even worse)
No load oscillate is a 200mV at 245kHz signal, that might be ok, but it's probably not helping the noise floor of the total system having those all squarbling away.. ?
EVP2_3v3_LDO_Oscillate_NoL.png
1478 x 793 - 72K
EVP2_3v3_LDO_Oscillate_40mA.png
1478 x 793 - 106K

Comments

  • RaymanRayman Posts: 14,646
    what's a CL?

    Are you saying not to use the VIO power on each I/O header?
  • VonSzarvasVonSzarvas Posts: 3,450
    This is not the designed use of the 3V3 LDOs. They should be jumpered to power the P2 I/O pins, and then VIO power can be obtained cleanly at the edge headers.

    In the case of no-load, the 200mV must be related to the measuring technique. An unloaded LDO of this type will not exhibit such ripple, and more importantly, will not impact VIN beyond the VIN cap. Ie. with the LDO output disconnected, it is not connected to anything and will not squarble anything.

    I believe this is a red herring.
  • Phil Pilgrim (PhiPi)Phil Pilgrim (PhiPi) Posts: 23,514
    Rayman wrote:
    what's a CL?
    I think he means "capacitive load," but I'm not sure.

    -Phil
  • cgraceycgracey Posts: 14,152
    edited 2018-12-27 23:19
    Yes, when the jumper is in the position to select the LDO regulator, it is then that the output bypass caps are connected. Before that, the quiescent draw through that regulator is probably on the order of a hundred microamps, or less.
  • jmgjmg Posts: 15,173
    edited 2018-12-27 23:16
    VonSzarvas wrote: »
    In the case of no-load, the 200mV must be related to the measuring technique. An unloaded LDO of this type will not exhibit such ripple..

    Sounds a bold and sweeping claim - have you actually applied a scope, to check such a claim ?

    Rayman wrote: »
    what's a CL?
    CL is the load capacitance such LDO require for stability. The PCB is designed such that CL is missing from the LDO, until the jumper is moved.
    Rayman wrote: »
    Are you saying not to use the VIO power on each I/O header?
    No, just that it needs care around the pins labeled 3v3 on the board.
    It may have a LDO regulator, and be labelled 3v3, but that is only for jumper-to-P2 special case use (adds the CL)
    A general user might expect a pin labeled 3v3 from a LDO to mean it is available as regulated 3.3v (eg to power a oscillator module)
  • TubularTubular Posts: 4,702
    When experimenting yesterday I noticed VGA looked better from the 3v3 "big switcher" compared with the 3v3 LDO, and wondered why (minimum load)? You can see this on solid color fill areas of the vga

    I was going to add a 1/4 watt load resistor today and see if it improves things

    This is all part of "the learning"...

  • jmgjmg Posts: 15,173
    Tubular wrote: »
    When experimenting yesterday I noticed VGA looked better from the 3v3 "big switcher" compared with the 3v3 LDO, and wondered why (minimum load)? You can see this on solid color fill areas of the vga

    I was going to add a 1/4 watt load resistor today and see if it improves things

    This is all part of "the learning"...
    That's a little unexpected, as usually you would hope the low noise LDO was the best supply to use. Maybe check with a scope to see if it is unstable ? What was the exact effect ?
    The 3v3 SMPS cycle skips at low loads, and seem to need ~ 100mA (33R) to change to every-cycle regulation.

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