Cluso,
The filter work is independent of the drifting noise problem, although it does have a big impact on high frequency noise. It's a nice new feature, or two, going into the Prop2.
The drifting noise is a separate concern that, currently, no one is pursuing. I intend to have a shot at it once I get an ES board.
PS: An improvement on high frequency noise was also made by the ES board over the P2D2 board.
. To me, it seems that you/others are trying to solve a problem that is not sufficiently understood by throwing all sorts of software solutions to the problem and then trying to make the hardware implement them.
The filter is fully usable for external ADC's, so the effort is far from wasted.
Not only that, the filter is tested on real P2 ADC streams, and improves those too.
Any residual noise issues in the PAD Ring itself, cannot be solved in this Verilog pass, so I'd say Chip is doing the right thing in improving the silicon, to allow faster ADC rates.
Chip,
I haven't been properly following the ADC saga, so this may be way off base...
There is some noise problem that shows up every 7-8 bits???
Could this possibly be some sort of sign extension bug???
I am not convinced you have got to the root cause of the ADC problems. To me, it seems that you/others are trying to solve a problem that is not sufficiently understood by throwing all sorts of software solutions to the problem and then trying to make the hardware implement them.
IMHO weeks have been wasted that could have been better spent on testing the P2, and/or writing things that really matter much more such as SPIN2 etc.
Cluso, there are bandwidth and noise limitations of the ADC, but I wouldn't call them problems. We are getting 13-bit conversions in 128 clocks, so that's pretty good.
I am running simulations tonight of the ADC, changing some values in the analog front-end to speed things up. I can make it settle full-scale input changes in 20ns with shorter, narrower transistors, but they are not as linear as the big ones in there now. Using smaller transistors would get our bandwidth up, but the ADC would need to be clocked at least 50MHz and there would be less linearity than we have now, maybe good for 8..10 bits, though. We really need TWO modes, one high-bandwidth and one low-bandwidth and precise (like we have now).
As it's currently designed, without any important modifications, even if you could output the analog residue, for further processing, due to bandwidht limitations it would not lead to any significative improvement, perhaps 1, 1.5 bits, at the cost of some cumbersome solutions, and the introduction of other non-linearities that the extra stage would not be able to take care off.
It would be like taking hours to traverse a slow-flowing and swampy river to jump-step right into a quicksand pitfall.
I am running simulations tonight of the ADC, changing some values in the analog front-end to speed things up. I can make it settle full-scale input changes in 20ns with shorter, narrower transistors, but they are not as linear as the big ones in there now. Using smaller transistors would get our bandwidth up, but the ADC would need to be clocked at least 50MHz and there would be less linearity than we have now, maybe good for 8..10 bits, though. We really need TWO modes, one high-bandwidth and one low-bandwidth and precise (like we have now).
Is there actually some intent now for some analog parts to be changed in the next rev? Or is this work you are doing only for a future P2 variant, and not the upcoming revB spin? I thought it was only logic changes possible for that.
Cluso,
The filter work is independent of the drifting noise problem, although it does have a big impact on high frequency noise. It's a nice new feature, or two, going into the Prop2.
The drifting noise is a separate concern that, currently, no one is pursuing. I intend to have a shot at it once I get an ES board.
PS: An improvement on high frequency noise was also made by the ES board over the P2D2 board.
That is likely because Chip has not fitted the bypass capacitors on the P2D2 board. Last pic I saw didn't have them fitted.
No. But I suspect that doesn't exclude it if there was a super improvement found.
Looks to me like Parallax is on a program with On. To me, that means spinning up this chip for production. Once that is all done, variants can be done.
Right now, it appears Chip is working hard to really understand the noise on all fronts. Goal would be to make this chip the best it can be. File the knowledge away for a future opportunity.
I am running simulations tonight of the ADC, changing some values in the analog front-end to speed things up. I can make it settle full-scale input changes in 20ns with shorter, narrower transistors, but they are not as linear as the big ones in there now. Using smaller transistors would get our bandwidth up, but the ADC would need to be clocked at least 50MHz and there would be less linearity than we have now, maybe good for 8..10 bits, though. We really need TWO modes, one high-bandwidth and one low-bandwidth and precise (like we have now).
Is there actually some intent now for some analog parts to be changed in the next rev? Or is this work you are doing only for a future P2 variant, and not the upcoming revB spin? I thought it was only logic changes possible for that.
I am resizing some PMOS devices in the ADC's analog front-end to increase its bandwidth. I'm trying to figure out how this will affect signal distortion.
Cluso,
The filter work is independent of the drifting noise problem, although it does have a big impact on high frequency noise. It's a nice new feature, or two, going into the Prop2.
The drifting noise is a separate concern that, currently, no one is pursuing. I intend to have a shot at it once I get an ES board.
PS: An improvement on high frequency noise was also made by the ES board over the P2D2 board.
That is likely because Chip has not fitted the bypass capacitors on the P2D2 board. Last pic I saw didn't have them fitted.
This is true. I only have one cap for VDD and one cap for VIO on my P2D2 board. It still works really well. That's certainly the main reason why I'm getting lower noise on the P2 Eval board. I should have thought to point that out earlier.
A neat trick from all this would be to route any input(s) to the builtin scope or logic analyzer and output the result to HDMI or LCD. Then pick and choose any input to watch.
I am resizing some PMOS devices in the ADC's analog front-end to increase its bandwidth. I'm trying to figure out how this will affect signal distortion.
Ok thanks for letting us all know Chip. Hope anything that is tweaked is safe and might buy us some bandwidth increase for perhaps even allowing analog video sampling at a reasonable quality even if monochrome. That would be pretty nice to have. I can imagine some robotics uses with cheap cameras etc. Also drone stuff perhaps and any other applications that might need overlays.
All night, I've been working on the ADC design to see what can be done to improve its bandwidth.
It turns out that two PMOS devices have most everything to do with the analog front-end performance, along with an RC filter on the output of a transconductance amp that drives their gates. In the current design, these PMOS's are big (width=12um, length=3.7um) and very linear. Smaller would be faster, but less linear. Linearity doesn't matter so much if the integrator voltage stays in a tight band, which happens at higher frequency. Right now, the ADC's work down to 1MHz, and all the way up. However, at high frequency, the bitstream gets clumpy because the integrator voltage is only changing by ~4mV per clock cycle and the inverter sense amp doesn't see much difference, so it doesn't switch on every clock.
I did a bunch of experiments with those two PMOS devices, taking them all the way down to 2um x 2um. They work much faster now, but are not as linear. I was able to improve the performance a good amount, but the biggest difference comes from reducing the integrator cap to 1/8th its current size.
In my simulations, I've been running the ADC at 300MHz while inputting a rail-to-rail 5MHz signal.
Here is a simulation of the tuned-up front-end with 1/8th the integrator cap, to allow more voltage swing. I need to do more simulations to determine if this front-end fix would be safe to do. I put this pic first because it shows what each trace is:
Here is the current design with 1/8th the integrator cap. This would be a very safe change to make in the next silicon:
And here is the ADC as it is now in the P2 silicon:
…. those two PMOS devices, taking them all the way down to 2um x 2um. They work much faster now, but are not as linear.
In my simulations, I've been running the ADC at 300MHz while inputting a rail-to-rail 5MHz signal.
O.K., so what is the risk? Is there a possibility of inducing a Van Der Pol instability in the sigma delta modulator, if the cap is too small; or (by guess and by golly) if the PMOS channel gets too noisy because of geometry issues and how they effect turbulence in the carrier flow? Thinking of "holes" in PMOS channel as balls in a pinball machine, and the doping atoms as the bumpers - classical statistical mechanics says "more turbulent" because of less averaging. Now add some feedback and it looks like the reconstructed 4th order with RC has a strong 9th harmonic, which for a 5 Mhz fundamental would equal 45 Mhz. In the tuned up design this looks best, subjectively; but I am not an expert here; or else if I am, then heaven help us! Well. since fools rush in -- here are some more observations …
1. On the turned up front end the balance voltage looks perfect! Similar to what a so called "2T-pulse" looks like in NTSC video - check out line 18 sometime of the old fashioned analog vertical interval test signals used in something called "the composite test signal" The "2T" pulse was chosen for its particular "goldilocks" properties, in part because a "T" pulse might cause a buzz in the audio if the low pass filtering (a brick wall type filter) in the transmitter modulator didn't do a proper job; but also because of possible distortions in the receiver, etc. So even though its easier to set up the group delay on a transmitter, etc., with a pulse that has Nyquist style, sin(x)/x like ringing - it in the FCC standards that that should be avoided. And besides that; the "2T" pulse more accurately replicates the type of signal that you expect to see from a single pixel when focus and spot size are taken in account with old time vidicon or saticon tubes.
2. On the "current design with smaller cap" (original front end?" it is clear from the image Q:GND:V that the waveform is slew rate limited; most likely because of the front end and not because of and inability of the modulator to keep up - that is to say - if what is really happening is that you are getting a 45 Mhz oscillation or thereabouts and that what the 300 Mhz slicer then does is that it guesses at where the time slices are with 3.3nSec resolution? Useful trivia - if you do the math, you will find that the "relative clock slip" if you wanted to generate broadcast FM with phase modulation is actually on the order of femto-seconds per cycle. I guess what I am asking then is - whether the "reconstructed" input is the idealized input before decimation at 300Mhz by the slicer/flip flop/latch or whatever makes a bitstream.
And in other news - I am still experimenting with minimal logic SIMD like filtering of simulated bit streams; and what can be extracted from time under ideal conditions. Here is a still buggy but mostly functional test of the 32 bits at a time to 8 bytes of sinc^N and decimated by 8 data. So I am wondering what the 45Mhz component will look like in the bitstream; …
...
R0:10111011101110111011101110111011 R1/2: 1 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4
R0:10111011101110111011101110111011 R1/2: 1 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4
R0:10111011101110111011101110111011 R1/2: 1 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4
R0:10111011101110111011101110111011 R1/2: 1 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4
R0:11001100110011001100110011001100 R1/2: 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1
R0:11001100110011001100110011001100 R1/2: 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1
R0:11001100110011001100110011001100 R1/2: 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1
R0:11001100110011001100110011001100 R1/2: 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1
R0:11001100110011001100110011001100 R1/2: 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1
R0:11001100110011001100110011001100 R1/2: 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1
R0:11001100110011001100110011001100 R1/2: 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1
R0:11001100110011001100110011001100 R1/2: 3 1 3 1 3 1 3 1 3 1 3 1 3 1 3 1
R0:11011101110111011101110111011101 R1/2: 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
R0:11011101110111011101110111011101 R1/2: 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
R0:11011101110111011101110111011101 R1/2: 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
R0:11011101110111011101110111011101 R1/2: 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
R0:11011101110111011101110111011101 R1/2: 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
R0:11011101110111011101110111011101 R1/2: 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
R0:11011101110111011101110111011101 R1/2: 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
R0:11011101110111011101110111011101 R1/2: 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
R0:11101110111011101110111011101110 R1/2: 3 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2
R0:11101110111011101110111011101110 R1/2: 3 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2
R0:11101110111011101110111011101110 R1/2: 3 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2
R0:11101110111011101110111011101110 R1/2: 3 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2
R0:11101110111011101110111011101110 R1/2: 3 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2
R0:11101110111011101110111011101110 R1/2: 3 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2
R0:11101110111011101110111011101110 R1/2: 3 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2
R0:11101110111011101110111011101110 R1/2: 3 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2
R0:11111111111111111111111111111111 R1/2: 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
R0:11111111111111111111111111111111 R1/2: 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
R0:11111111111111111111111111111111 R1/2: 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
R0:11111111111111111111111111111111 R1/2: 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
R0:11111111111111111111111111111111 R1/2: 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
R0:11111111111111111111111111111111 R1/2: 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
R0:11111111111111111111111111111111 R1/2: 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
R0:11111111111111111111111111111111 R1/2: 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
BIT TEST - BYTES
R0:00000000000000000000000000000000 R3/4: 0 0 0 0 0 0 0 0
R0:00000000000000000000000000000000 R3/4: 0 0 0 0 0 0 0 0
R0:00000000000000000000000000000000 R3/4: 0 0 0 0 0 0 0 0
R0:00000000000000000000000000000000 R3/4: 0 0 0 0 0 0 0 0
R0:00000000000000000000000000000000 R3/4: 0 0 0 0 0 0 0 0
R0:00000000000000000000000000000000 R3/4: 0 0 0 0 0 0 0 0
R0:00000000000000000000000000000000 R3/4: 0 0 0 0 0 0 0 0
R0:00000000000000000000000000000000 R3/4: 0 0 0 0 0 0 0 0
R0:00010001000100010001000100010001 R3/4: 0 4 4 4 4 4 4 4
R0:00010001000100010001000100010001 R3/4: 0 4 4 4 4 4 4 4
R0:00010001000100010001000100010001 R3/4: 0 4 4 4 4 4 4 4
R0:00010001000100010001000100010001 R3/4: 0 4 4 4 4 4 4 4
R0:00010001000100010001000100010001 R3/4: 0 4 4 4 4 4 4 4
R0:00010001000100010001000100010001 R3/4: 0 4 4 4 4 4 4 4
R0:00010001000100010001000100010001 R3/4: 0 4 4 4 4 4 4 4
R0:00010001000100010001000100010001 R3/4: 0 4 4 4 4 4 4 4
R0:00100010001000100010001000100010 R3/4: 0 2 4 4 4 4 4 4
R0:00100010001000100010001000100010 R3/4: 0 2 4 4 4 4 4 4
R0:00100010001000100010001000100010 R3/4: 0 2 4 4 4 4 4 4
R0:00100010001000100010001000100010 R3/4: 0 2 4 4 4 4 4 4
R0:00100010001000100010001000100010 R3/4: 0 2 4 4 4 4 4 4
R0:00100010001000100010001000100010 R3/4: 0 2 4 4 4 4 4 4
R0:00100010001000100010001000100010 R3/4: 0 2 4 4 4 4 4 4
R0:00100010001000100010001000100010 R3/4: 0 2 4 4 4 4 4 4
R0:00110011001100110011001100110011 R3/4: 0 6 8 8 8 8 8 8
R0:00110011001100110011001100110011 R3/4: 0 6 8 8 8 8 8 8
R0:00110011001100110011001100110011 R3/4: 0 6 8 8 8 8 8 8
R0:00110011001100110011001100110011 R3/4: 0 6 8 8 8 8 8 8
R0:00110011001100110011001100110011 R3/4: 0 6 8 8 8 8 8 8
R0:00110011001100110011001100110011 R3/4: 0 6 8 8 8 8 8 8
R0:00110011001100110011001100110011 R3/4: 0 6 8 8 8 8 8 8
R0:00110011001100110011001100110011 R3/4: 0 6 8 8 8 8 8 8
R0:01000100010001000100010001000100 R3/4: 2 2 4 4 4 4 4 4
R0:01000100010001000100010001000100 R3/4: 2 2 4 4 4 4 4 4
R0:01000100010001000100010001000100 R3/4: 2 2 4 4 4 4 4 4
R0:01000100010001000100010001000100 R3/4: 2 2 4 4 4 4 4 4
R0:01000100010001000100010001000100 R3/4: 2 2 4 4 4 4 4 4
R0:01000100010001000100010001000100 R3/4: 2 2 4 4 4 4 4 4
R0:01000100010001000100010001000100 R3/4: 2 2 4 4 4 4 4 4
R0:01000100010001000100010001000100 R3/4: 2 2 4 4 4 4 4 4
R0:01010101010101010101010101010101 R3/4: 2 6 8 8 8 8 8 8
R0:01010101010101010101010101010101 R3/4: 2 6 8 8 8 8 8 8
R0:01010101010101010101010101010101 R3/4: 2 6 8 8 8 8 8 8
R0:01010101010101010101010101010101 R3/4: 2 6 8 8 8 8 8 8
R0:01010101010101010101010101010101 R3/4: 2 6 8 8 8 8 8 8
R0:01010101010101010101010101010101 R3/4: 2 6 8 8 8 8 8 8
R0:01010101010101010101010101010101 R3/4: 2 6 8 8 8 8 8 8
R0:01010101010101010101010101010101 R3/4: 2 6 8 8 8 8 8 8
R0:01100110011001100110011001100110 R3/4: 2 4 8 8 8 8 8 8
R0:01100110011001100110011001100110 R3/4: 2 4 8 8 8 8 8 8
R0:01100110011001100110011001100110 R3/4: 2 4 8 8 8 8 8 8
R0:01100110011001100110011001100110 R3/4: 2 4 8 8 8 8 8 8
R0:01100110011001100110011001100110 R3/4: 2 4 8 8 8 8 8 8
R0:01100110011001100110011001100110 R3/4: 2 4 8 8 8 8 8 8
R0:01100110011001100110011001100110 R3/4: 2 4 8 8 8 8 8 8
R0:01100110011001100110011001100110 R3/4: 2 4 8 8 8 8 8 8
R0:01110111011101110111011101110111 R3/4: 2 8 c c c c c c
R0:01110111011101110111011101110111 R3/4: 2 8 c c c c c c
R0:01110111011101110111011101110111 R3/4: 2 8 c c c c c c
R0:01110111011101110111011101110111 R3/4: 2 8 c c c c c c
R0:01110111011101110111011101110111 R3/4: 2 8 c c c c c c
R0:01110111011101110111011101110111 R3/4: 2 8 c c c c c c
R0:01110111011101110111011101110111 R3/4: 2 8 c c c c c c
R0:01110111011101110111011101110111 R3/4: 2 8 c c c c c c
R0:10001000100010001000100010001000 R3/4: 1 3 4 4 4 4 4 4
R0:10001000100010001000100010001000 R3/4: 1 3 4 4 4 4 4 4
R0:10001000100010001000100010001000 R3/4: 1 3 4 4 4 4 4 4
R0:10001000100010001000100010001000 R3/4: 1 3 4 4 4 4 4 4
R0:10001000100010001000100010001000 R3/4: 1 3 4 4 4 4 4 4
R0:10001000100010001000100010001000 R3/4: 1 3 4 4 4 4 4 4
R0:10001000100010001000100010001000 R3/4: 1 3 4 4 4 4 4 4
R0:10001000100010001000100010001000 R3/4: 1 3 4 4 4 4 4 4
R0:10011001100110011001100110011001 R3/4: 1 7 8 8 8 8 8 8
R0:10011001100110011001100110011001 R3/4: 1 7 8 8 8 8 8 8
R0:10011001100110011001100110011001 R3/4: 1 7 8 8 8 8 8 8
R0:10011001100110011001100110011001 R3/4: 1 7 8 8 8 8 8 8
R0:10011001100110011001100110011001 R3/4: 1 7 8 8 8 8 8 8
R0:10011001100110011001100110011001 R3/4: 1 7 8 8 8 8 8 8
R0:10011001100110011001100110011001 R3/4: 1 7 8 8 8 8 8 8
R0:10011001100110011001100110011001 R3/4: 1 7 8 8 8 8 8 8
R0:10101010101010101010101010101010 R3/4: 1 5 8 8 8 8 8 8
R0:10101010101010101010101010101010 R3/4: 1 5 8 8 8 8 8 8
R0:10101010101010101010101010101010 R3/4: 1 5 8 8 8 8 8 8
R0:10101010101010101010101010101010 R3/4: 1 5 8 8 8 8 8 8
R0:10101010101010101010101010101010 R3/4: 1 5 8 8 8 8 8 8
R0:10101010101010101010101010101010 R3/4: 1 5 8 8 8 8 8 8
R0:10101010101010101010101010101010 R3/4: 1 5 8 8 8 8 8 8
R0:10101010101010101010101010101010 R3/4: 1 5 8 8 8 8 8 8
R0:10111011101110111011101110111011 R3/4: 1 9 c c c c c c
R0:10111011101110111011101110111011 R3/4: 1 9 c c c c c c
R0:10111011101110111011101110111011 R3/4: 1 9 c c c c c c
R0:10111011101110111011101110111011 R3/4: 1 9 c c c c c c
R0:10111011101110111011101110111011 R3/4: 1 9 c c c c c c
R0:10111011101110111011101110111011 R3/4: 1 9 c c c c c c
R0:10111011101110111011101110111011 R3/4: 1 9 c c c c c c
R0:10111011101110111011101110111011 R3/4: 1 9 c c c c c c
R0:11001100110011001100110011001100 R3/4: 3 5 8 8 8 8 8 8
R0:11001100110011001100110011001100 R3/4: 3 5 8 8 8 8 8 8
R0:11001100110011001100110011001100 R3/4: 3 5 8 8 8 8 8 8
R0:11001100110011001100110011001100 R3/4: 3 5 8 8 8 8 8 8
R0:11001100110011001100110011001100 R3/4: 3 5 8 8 8 8 8 8
R0:11001100110011001100110011001100 R3/4: 3 5 8 8 8 8 8 8
R0:11001100110011001100110011001100 R3/4: 3 5 8 8 8 8 8 8
R0:11001100110011001100110011001100 R3/4: 3 5 8 8 8 8 8 8
R0:11011101110111011101110111011101 R3/4: 3 9 c c c c c c
R0:11011101110111011101110111011101 R3/4: 3 9 c c c c c c
R0:11011101110111011101110111011101 R3/4: 3 9 c c c c c c
R0:11011101110111011101110111011101 R3/4: 3 9 c c c c c c
R0:11011101110111011101110111011101 R3/4: 3 9 c c c c c c
R0:11011101110111011101110111011101 R3/4: 3 9 c c c c c c
R0:11011101110111011101110111011101 R3/4: 3 9 c c c c c c
R0:11011101110111011101110111011101 R3/4: 3 9 c c c c c c
R0:11101110111011101110111011101110 R3/4: 3 7 c c c c c c
R0:11101110111011101110111011101110 R3/4: 3 7 c c c c c c
R0:11101110111011101110111011101110 R3/4: 3 7 c c c c c c
R0:11101110111011101110111011101110 R3/4: 3 7 c c c c c c
R0:11101110111011101110111011101110 R3/4: 3 7 c c c c c c
R0:11101110111011101110111011101110 R3/4: 3 7 c c c c c c
R0:11101110111011101110111011101110 R3/4: 3 7 c c c c c c
R0:11101110111011101110111011101110 R3/4: 3 7 c c c c c c
R0:11111111111111111111111111111111 R3/4: 3 b 10 10 10 10 10 10
R0:11111111111111111111111111111111 R3/4: 3 b 10 10 10 10 10 10
R0:11111111111111111111111111111111 R3/4: 3 b 10 10 10 10 10 10
R0:11111111111111111111111111111111 R3/4: 3 b 10 10 10 10 10 10
R0:11111111111111111111111111111111 R3/4: 3 b 10 10 10 10 10 10
R0:11111111111111111111111111111111 R3/4: 3 b 10 10 10 10 10 10
R0:11111111111111111111111111111111 R3/4: 3 b 10 10 10 10 10 10
R0:11111111111111111111111111111111 R3/4: 3 b 10 10 10 10 10 10
All night, I've been working on the ADC design to see what can be done to improve its bandwidth.
Hmm... nice, but also very niche, and also risks decreasing the lower frequency performance, where far more customers will be operating.
We still do not have a DNL/INL plot of the present ADC, or the filter tested with external ADC for confirmation.
Key question: What significant large markets do these tweaks to ADC open, that were not available before ?
I would pause outer ring changes until P3, and focus on better P2 test coverage.
All night, I've been working on the ADC design to see what can be done to improve its bandwidth.
Hmm... nice, but also very niche, and also risks decreasing the lower frequency performance, where far more customers will be operating.
We still do not have a DNL/INL plot of the present ADC, or the filter tested with external ADC for confirmation.
Key question: What significant large markets do these tweaks to ADC open, that were not available before ?
I would pause outer ring changes until P3, and focus on better P2 test coverage.
If the ADCs need to be run at 10MHz+, instead of 1MHz+, do you think that's a problem?
I keep wondering if decreasing the integrator capacitance can cause any loss. I don't think so, but I'm not sure. What do you think? I suppose everything just cancels out.
I don't want to mess with the front-end, after all, because all that tuning I did required way less dampening than is there now, and slight adjustments cause it to ring on transitions. What we have now is very robust on the front-end, and not that much lower in bandwidth. Reducing the integrator cap is the biggest win, by far. Maybe I can make it selectable between what it is now and 1/8th.
I keep wondering if decreasing the integrator capacitance can cause any loss. I don't think so, but I'm not sure.
Depends what you mean by loss ?
There is charge injection from unwanted sources to worry about, and lower frequency noise is likely worse, as the node impedance is now that bit higher.
The rest of the P2 die is an aggressor in all of this...
If you really want to try this, I'd suggest change of just (say) 4 pin cells, being those under the 'lost' upper pins. (TX/RX/Boot)
That way, you have no risk of breaking existing ADC, which actually works, and you can test the ideas on real silicon.
Any news on logic size with Tukey in the smart pins?
If it's just too big to fit, could we have a mode where groups of eight ADC bits from each of four pins can be read/streamed in one long?
Putting a Tukey into every smart pin, taking advantage of the existing flops, was smaller than putting half that many into the cogs. Only by a little bit, though.
Comments
The filter work is independent of the drifting noise problem, although it does have a big impact on high frequency noise. It's a nice new feature, or two, going into the Prop2.
The drifting noise is a separate concern that, currently, no one is pursuing. I intend to have a shot at it once I get an ES board.
PS: An improvement on high frequency noise was also made by the ES board over the P2D2 board.
The filter is fully usable for external ADC's, so the effort is far from wasted.
Not only that, the filter is tested on real P2 ADC streams, and improves those too.
Any residual noise issues in the PAD Ring itself, cannot be solved in this Verilog pass, so I'd say Chip is doing the right thing in improving the silicon, to allow faster ADC rates.
You are right about there being plenty more to test. On that note, I don't see the next fab run starting before April.
Cluso, there are bandwidth and noise limitations of the ADC, but I wouldn't call them problems. We are getting 13-bit conversions in 128 clocks, so that's pretty good.
I am running simulations tonight of the ADC, changing some values in the analog front-end to speed things up. I can make it settle full-scale input changes in 20ns with shorter, narrower transistors, but they are not as linear as the big ones in there now. Using smaller transistors would get our bandwidth up, but the ADC would need to be clocked at least 50MHz and there would be less linearity than we have now, maybe good for 8..10 bits, though. We really need TWO modes, one high-bandwidth and one low-bandwidth and precise (like we have now).
It would be like taking hours to traverse a slow-flowing and swampy river to jump-step right into a quicksand pitfall.
Is there actually some intent now for some analog parts to be changed in the next rev? Or is this work you are doing only for a future P2 variant, and not the upcoming revB spin? I thought it was only logic changes possible for that.
That is likely because Chip has not fitted the bypass capacitors on the P2D2 board. Last pic I saw didn't have them fitted.
No. But I suspect that doesn't exclude it if there was a super improvement found.
Looks to me like Parallax is on a program with On. To me, that means spinning up this chip for production. Once that is all done, variants can be done.
Right now, it appears Chip is working hard to really understand the noise on all fronts. Goal would be to make this chip the best it can be. File the knowledge away for a future opportunity.
I am resizing some PMOS devices in the ADC's analog front-end to increase its bandwidth. I'm trying to figure out how this will affect signal distortion.
This is true. I only have one cap for VDD and one cap for VIO on my P2D2 board. It still works really well. That's certainly the main reason why I'm getting lower noise on the P2 Eval board. I should have thought to point that out earlier.
If it's just too big to fit, could we have a mode where groups of eight ADC bits from each of four pins can be read/streamed in one long?
I still haven't heard back from Wendy at ON Semi.
Ok thanks for letting us all know Chip. Hope anything that is tweaked is safe and might buy us some bandwidth increase for perhaps even allowing analog video sampling at a reasonable quality even if monochrome. That would be pretty nice to have. I can imagine some robotics uses with cheap cameras etc. Also drone stuff perhaps and any other applications that might need overlays.
It turns out that two PMOS devices have most everything to do with the analog front-end performance, along with an RC filter on the output of a transconductance amp that drives their gates. In the current design, these PMOS's are big (width=12um, length=3.7um) and very linear. Smaller would be faster, but less linear. Linearity doesn't matter so much if the integrator voltage stays in a tight band, which happens at higher frequency. Right now, the ADC's work down to 1MHz, and all the way up. However, at high frequency, the bitstream gets clumpy because the integrator voltage is only changing by ~4mV per clock cycle and the inverter sense amp doesn't see much difference, so it doesn't switch on every clock.
I did a bunch of experiments with those two PMOS devices, taking them all the way down to 2um x 2um. They work much faster now, but are not as linear. I was able to improve the performance a good amount, but the biggest difference comes from reducing the integrator cap to 1/8th its current size.
In my simulations, I've been running the ADC at 300MHz while inputting a rail-to-rail 5MHz signal.
Here is a simulation of the tuned-up front-end with 1/8th the integrator cap, to allow more voltage swing. I need to do more simulations to determine if this front-end fix would be safe to do. I put this pic first because it shows what each trace is:
Here is the current design with 1/8th the integrator cap. This would be a very safe change to make in the next silicon:
And here is the ADC as it is now in the P2 silicon:
O.K., so what is the risk? Is there a possibility of inducing a Van Der Pol instability in the sigma delta modulator, if the cap is too small; or (by guess and by golly) if the PMOS channel gets too noisy because of geometry issues and how they effect turbulence in the carrier flow? Thinking of "holes" in PMOS channel as balls in a pinball machine, and the doping atoms as the bumpers - classical statistical mechanics says "more turbulent" because of less averaging. Now add some feedback and it looks like the reconstructed 4th order with RC has a strong 9th harmonic, which for a 5 Mhz fundamental would equal 45 Mhz. In the tuned up design this looks best, subjectively; but I am not an expert here; or else if I am, then heaven help us! Well. since fools rush in -- here are some more observations …
1. On the turned up front end the balance voltage looks perfect! Similar to what a so called "2T-pulse" looks like in NTSC video - check out line 18 sometime of the old fashioned analog vertical interval test signals used in something called "the composite test signal" The "2T" pulse was chosen for its particular "goldilocks" properties, in part because a "T" pulse might cause a buzz in the audio if the low pass filtering (a brick wall type filter) in the transmitter modulator didn't do a proper job; but also because of possible distortions in the receiver, etc. So even though its easier to set up the group delay on a transmitter, etc., with a pulse that has Nyquist style, sin(x)/x like ringing - it in the FCC standards that that should be avoided. And besides that; the "2T" pulse more accurately replicates the type of signal that you expect to see from a single pixel when focus and spot size are taken in account with old time vidicon or saticon tubes.
2. On the "current design with smaller cap" (original front end?" it is clear from the image Q:GND:V that the waveform is slew rate limited; most likely because of the front end and not because of and inability of the modulator to keep up - that is to say - if what is really happening is that you are getting a 45 Mhz oscillation or thereabouts and that what the 300 Mhz slicer then does is that it guesses at where the time slices are with 3.3nSec resolution? Useful trivia - if you do the math, you will find that the "relative clock slip" if you wanted to generate broadcast FM with phase modulation is actually on the order of femto-seconds per cycle. I guess what I am asking then is - whether the "reconstructed" input is the idealized input before decimation at 300Mhz by the slicer/flip flop/latch or whatever makes a bitstream.
And in other news - I am still experimenting with minimal logic SIMD like filtering of simulated bit streams; and what can be extracted from time under ideal conditions. Here is a still buggy but mostly functional test of the 32 bits at a time to 8 bytes of sinc^N and decimated by 8 data. So I am wondering what the 45Mhz component will look like in the bitstream; …
We still do not have a DNL/INL plot of the present ADC, or the filter tested with external ADC for confirmation.
Key question: What significant large markets do these tweaks to ADC open, that were not available before ?
I would pause outer ring changes until P3, and focus on better P2 test coverage.
If the ADCs need to be run at 10MHz+, instead of 1MHz+, do you think that's a problem?
I keep wondering if decreasing the integrator capacitance can cause any loss. I don't think so, but I'm not sure. What do you think? I suppose everything just cancels out.
I don't want to mess with the front-end, after all, because all that tuning I did required way less dampening than is there now, and slight adjustments cause it to ring on transitions. What we have now is very robust on the front-end, and not that much lower in bandwidth. Reducing the integrator cap is the biggest win, by far. Maybe I can make it selectable between what it is now and 1/8th.
Depends what you mean by loss ?
There is charge injection from unwanted sources to worry about, and lower frequency noise is likely worse, as the node impedance is now that bit higher.
The rest of the P2 die is an aggressor in all of this...
If you really want to try this, I'd suggest change of just (say) 4 pin cells, being those under the 'lost' upper pins. (TX/RX/Boot)
That way, you have no risk of breaking existing ADC, which actually works, and you can test the ideas on real silicon.
-Phil
The market of me liking it better.
Chip's inner Benevolent Dictator is coming out!
Awesome!
I really hope to someday have a reason to borrow that phrase!
C.W.
Nothing wrong with letting the inner perfectionist out once in a while.
-Phil
Putting a Tukey into every smart pin, taking advantage of the existing flops, was smaller than putting half that many into the cogs. Only by a little bit, though.
On each clock, the ADC bit is now used to add/subtract an 8-bit cosine value and an 8-bit sine value to/from the X and Y accumulators.
If we did a SINC2 by integrating the accumulators, and then took their periodic readings and computed diffs, might we double the ENOB of our readings?
And how would all this work with the adder terms and accumulators and final integrators being all signed?
This would, at least, get us around the lack-of-windowing problem that we already have in the Goertzel.