Streamer for digital pin sampling

Cluso99 · 2018-11-04 21:37

I would like to use the P2 streamer to sample I/O pins and am not sure where to start.
I have a separate cog that will wait for a que to log a sample of pins.

What i need to understand is how to setup the streamer to read 'n' samples of pins, where these samples will be saved, and if I can save a group of pins.

Can I sample P0-P31 (a long) each clock?

Is there any sample code to look at?

evanh · 2018-11-04 21:53

Here's a streamer config for 32-bit input:

%1111_xxxx_xppp_xxxx          -    32-pin -> WFLONG                    <none>

In the case of the pure input modes (top nibble = %1101..%1111), the %ppp field selects which pins will be captured on streamer input cycles:

%ppp : 000 = pins 31..0
001 = pins 39..8
010 = pins 47..16
011 = pins 55..24
100 = pins 63..32
101 = pins 7..0, 63..40
110 = pins 15..0, 63..48
111 = pins 23..0, 63..56

For the 1/2/4-bit WFBYTE submodes, extra %p bits below the %ppp field are use to select the bit, twit, or nibble within the byte selected by %ppp.

WFBYTE/WFWORD/WFLONG modes
On every NCO rollover, input pins are captured and a background WFBYTE/WFWORD/WFLONG is executed to store them into the hub.

It is necessary to do a WRFAST sometime beforehand, to ensure that the hub RAM FIFO is ready to receive data.

evanh · 2018-11-04 21:55

The Goertzel testing should help with general use of the streamers - https://forums.parallax.com/discussion/169210/goertzel-self-test/p1

cgracey · 2018-11-04 21:59

It is really simple, Cluso99. First, you set up the frequency and then you give it a command which includes how many samples to take. Of course, do a WRFAST first.

ozpropdev · 2018-11-04 22:36

Ray
Have a look at my P2 logic analyzer, it should help.
https://forums.parallax.com/discussion/163967/p123-a9-prop2-logic-analyzer

Cluso99 · 2018-11-05 02:31

Thanks for the link Brian. I'll look to see if it does what I want as it may well do, or else a simple mod may work.
I often just want to see what is happening on a group of pins. I can easily set something to start the sample off, and let it run for 'x' samples.
Hopefully it samples on every clock. I presume this is possible?

cgracey · 2018-11-05 03:04

The default frequency setting is $8000_0000, which causes something to happen on every clock.

Cluso99 · 2018-11-05 20:18

Code looks good Brian.
I expected the streamer part to be way more complex to setup. Should get some time to try it today.
Thanks Chip. Similar to P1 timer setup

Cluso99 · 2018-11-06 04:09

Here is a section of code to record 'sample_length' of P0-P31 or P32-P63 using the streamer into HUB RAM at 'samples'...

con
' Streams INA (32 bits) to hub.
                sample_length = 4000    'longs

dat             orgh
                org     0
...
                setxfrq ##$8000_0000    'sysclk sample rate
                wrfast  #0,##@samples
'                         %1111_xxxx_xppp_xxxx << 16 ppp=000 P00-31, =100 P32-63
'                         %1111_xxxx_xppp_xxxx << 16
'                                     000                                 P31-0
'                                     001                                 P39-8
'                                     010                                 P47-16
'                                     011                                 P55-24
'                                     100                                 P63-32
'                                     101                            P7-0+P63-40
'                                     110                           P15-0+P63-48
'                                     111                           P23-0+P63-56 
                xinit   ##%1111_0000_0000_0000 << 16 | sample_length,#0  'P00-31
'               xinit   ##%1111_0000_0100_0000 << 16 | sample_length,#0  'P32-63
                waitxfi
'*******************************************************************
                orgh    $4000
samples         long    0[sample_length]
'*******************************************************************

Cluso99 · 2018-11-06 05:46

Here is a complete program for sampling P0-31 or P32-63 and then outputting to the serial port using the ROM in-built commands to output in hex...

Cluso99 · 2018-11-14 00:43

Next question,
Using the streamer in writing pins to hub, if I just want to write 8 pins, I use WRBYTE.
The docs seem to imply that a byte is written to hub on every NCO rollover.

Does the hub address increment by 1 for each wrbyte?
And if I am streaming every clock, will the streamer/fifo pack the bytes up where necessary as the hub window is 8 clocks and each clock the window advances by a long address?

cgracey · 2018-11-14 01:30

Yes, it's all taken care of.

Cluso99 · 2018-11-17 10:11

In the VGA program, the hub accounts for half the screen. That's fine because if i display 2X it just wraps. So RDFAST is only executed once at the beginning.

If I want to change the buffer during the screen display, do I need to insert an FBLOCK instruction (D[31]=0) in between one of the line displays? Will it store the new values ready for the RDFAST count expiration?
eg At the start of the visible lines, execute an FBLOCK ##blockcount,##hubaddr and halfway thru the visible lines, execute another FBLOCK ##blockcount,##hubaddr2 where blockcount= 1080 /2 /64 /2 = 135/32 ??

cgracey · 2018-11-17 14:04

You can do FBLOCK right after RDFAST, but before the current block is completed. Not sure about your math, as I don't know your goal.

Cluso99 · 2018-11-17 22:45

Thanks Chip. I just wanted to confirm what I thought was the case.
I want to build the 1080 screen into sections - part graphics and part text. I want the whole 512KB HUB for screen buffer, so I will need to load up cogs/luts first, then clear hub for the buffer.

This is the "FUN" that we all love

And it's testing out the P2 in different ways.

Cluso99 · 2018-11-24 13:51

The following works for streaming 32-pins, 16-pins and 1-pin.

'' Sample P0-P31 using streamer to hub on every clock cycle...
                setxfrq ##$8000_0000                    'sysclk sample rate
                wrfast  #0,##@samples
'                         %1111_xxxx_xppp_xxxx << 16
'                                     000                                 P31-0
'                                     001                                 P39-8
'                                     010                                 P47-16
'                                     011                                 P55-24
'                                     100                                 P63-32
'                                     101                            P7-0+P63-40
'                                     110                           P15-0+P63-48
'                                     111                           P23-0+P63-56 
                xinit   ##%1111_0000_0000_0000 << 16 | sample_length,#0  'P00-31
'               xinit   ##%1111_0000_0100_0000 << 16 | sample_length,#0  'P32-63
'               xinit   ##%1110_0000_0000_0000 << 16 | sample_length,#0  'P00-15 (16 bits)
'               xinit   ##%1101_xxxx_xppp_pppx << 16 | sample_length,#0  'P00    (1 bit) wkg
                waitxfi

The following is in the document, but I am not following the explanation or get it to work for 8-bits, 4-bits or 2-bits

%1101_xxxx_xppp_pppx %r00 1-pin -> WFBYTE, r=reorder <none>
%1101_xxxx_xppp_ppxx %r01 2-pin -> WFBYTE, r=reorder <none>
%1101_xxxx_xppp_pxxx %r10 4-pin -> WFBYTE, r=reorder <none>
%1101_xxxx_xppp_xxxx %11 8-pin -> WFBYTE <none>

Anyone have it working in byte/nibble/nit modes?

cgracey · 2018-11-24 14:02

Cluso99, I found a strange bug in these modes, I believe, where your XINIT/XCONT/XZERO instruction cannot have D[2:0] clear. It seems to hang up the streamer.

Cluso99 · 2018-11-24 14:02

Solved...

                xinit   ##%1101_0000_0000_0000 << 16 | sample_length,#%00011  'P00-07 (8 bits)

Needed extra config bits in the #S operand. I was trying to put them in the #D command

jmg · 2018-11-24 21:34

cgracey wrote: »

Cluso99, I found a strange bug in these modes, I believe, where your XINIT/XCONT/XZERO instruction cannot have D[2:0] clear. It seems to hang up the streamer.

Does the 'solved' above merely avoid this bug ?

cgracey · 2018-11-24 22:00

jmg wrote: »

cgracey wrote: »

Cluso99, I found a strange bug in these modes, I believe, where your XINIT/XCONT/XZERO instruction cannot have D[2:0] clear. It seems to hang up the streamer.

Does the 'solved' above merely avoid this bug ?

Not sure, but the streamer is getting a big makeover. I'll need to recreate exactly what the problem was. It needs to be known for the current silicon.

Cluso99 · 2018-11-24 22:17

cgracey wrote: »

Cluso99, I found a strange bug in these modes, I believe, where your XINIT/XCONT/XZERO instruction cannot have D[2:0] clear. It seems to hang up the streamer.

I've probably avoided the bug accidentally as I've used the sample length in decimal as in 50, 200, etc.

Hope to combine my sampler with my VGA today. Wish me luck

ozpropdev · 2018-11-24 23:26

The streamer bug appears in 4/2/1 bit modes when DAC's are involved.

cgracey · 2018-11-24 23:48

ozpropdev wrote: »

The streamer bug appears in 4/2/1 bit modes when DAC's are involved.

There's another one, I believe, that has to do with WFBYTE 1/2/4-bit modes and count LSBs in D[2:0].

Streamer for digital pin sampling

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