Measuring P2 die temperature - ideas ?
jmg
Posts: 15,173
With the present thermal envelope on P2, knowing the die temperature is likely to be more important.
One possible pathway, is to use the TEST pin substrate/esd diode driven negative with a light current, and use that on-die diode as an indicator of temperature.
Q: To check if this is even feasible, can someone with a P2 device isolate TEST, and use a multimeter (diode range) to measure the -ve dirn diode drop (-0.6v), and then run various CLK speeds to change the die temperature ?
If that works, a part like onSemi's MAX1720 (SOT26+passives) can be used current fed/voltage starved to drive the diode ~ -100uA.
Then either MAX1720 V+ can be measured (should ~mirror -Vd) or the -Vd can feed to a Analog pin, via a resistor scaled to give ~ 0V at cold temps.
The on-chip resistor tolerance will matter here, as it forms a divider with the external resistor.
A benefit of the resistor ( >>10k) is it could connect to a non-boot-sensed SPI pin, to get a no-added-pin cost thermal sense path.
Other ideas :
Possible could be a part like NCT75MNR2G (OnSemi, i2c TempSense, 2x2mm0.5 ~ 26c) - but that needs i2c connections, and is not an on-die sense element.
They also have N34TS04, bumps to ~ 80c, but adds a 4kb EEPROM in a 2x3 package.
Or, use more of the Smart Pins, (10uA source, 100uA sink) & capacitor couple to TEST with a ~22~50k pulldown & use the cap as a voltage level shift
Example numbers here give
10uA Source C charge times (initial power up) - after power up, keep charge balance time > (10x Measure time). Vpin ~ +220mV during charge = LOW logic.
0.1uF 0.1u*3.3/10u = 33ms
0.33uF 0.33u*3.3/10u = 109ms
100uA sink C Measure time (100mV dV indicator) Analog voltage is initially Vio-Vd (Pulldown steals 27~12uA of the 100uA test drive)
0.1uF 0.1u*0.1/100u = 100us (Tcharge >> 1ms)
0.33uF 0.33u*0.1/100u = 330us (Tcharge >> 3.3ms)
Measure cost here is just 2 passives, but it does need a dedicated pin for P2-Temp reading.
If that does work, it makes a good skewed-current-drive use demonstration.
or, if the Resistor/Current source have stable & consistent enough tempco's, yet another smart-pin approach would be to use any/best mix of the termination choices of
1.5k/15k/150k & 1mA/100uA/10uA which I think are available going both ways (Hi & lo). That could apply to a SPI pin ?
One possible pathway, is to use the TEST pin substrate/esd diode driven negative with a light current, and use that on-die diode as an indicator of temperature.
Q: To check if this is even feasible, can someone with a P2 device isolate TEST, and use a multimeter (diode range) to measure the -ve dirn diode drop (-0.6v), and then run various CLK speeds to change the die temperature ?
If that works, a part like onSemi's MAX1720 (SOT26+passives) can be used current fed/voltage starved to drive the diode ~ -100uA.
Then either MAX1720 V+ can be measured (should ~mirror -Vd) or the -Vd can feed to a Analog pin, via a resistor scaled to give ~ 0V at cold temps.
The on-chip resistor tolerance will matter here, as it forms a divider with the external resistor.
A benefit of the resistor ( >>10k) is it could connect to a non-boot-sensed SPI pin, to get a no-added-pin cost thermal sense path.
Other ideas :
Possible could be a part like NCT75MNR2G (OnSemi, i2c TempSense, 2x2mm0.5 ~ 26c) - but that needs i2c connections, and is not an on-die sense element.
They also have N34TS04, bumps to ~ 80c, but adds a 4kb EEPROM in a 2x3 package.
Or, use more of the Smart Pins, (10uA source, 100uA sink) & capacitor couple to TEST with a ~22~50k pulldown & use the cap as a voltage level shift
Example numbers here give
10uA Source C charge times (initial power up) - after power up, keep charge balance time > (10x Measure time). Vpin ~ +220mV during charge = LOW logic.
0.1uF 0.1u*3.3/10u = 33ms
0.33uF 0.33u*3.3/10u = 109ms
100uA sink C Measure time (100mV dV indicator) Analog voltage is initially Vio-Vd (Pulldown steals 27~12uA of the 100uA test drive)
0.1uF 0.1u*0.1/100u = 100us (Tcharge >> 1ms)
0.33uF 0.33u*0.1/100u = 330us (Tcharge >> 3.3ms)
Measure cost here is just 2 passives, but it does need a dedicated pin for P2-Temp reading.
If that does work, it makes a good skewed-current-drive use demonstration.
or, if the Resistor/Current source have stable & consistent enough tempco's, yet another smart-pin approach would be to use any/best mix of the termination choices of
1.5k/15k/150k & 1mA/100uA/10uA which I think are available going both ways (Hi & lo). That could apply to a SPI pin ?
Comments
I do rather like the idea of seeing if an ESD diode or the Smart Pin characteristics can be leveraged to attempt to get a rough measure of die temp.
More seriously I think there will be analog things that reveal temperature, we don't know what measurement modes yet.
First, you have to choose what the device is mounted on, a 2 layer board like P2D2, or a 4 layer board or perhaps your interested in comparing the two.
There's two ways to go at this. The first way, you just need a pencil and paper and perhaps a computer. If you assume a uniform die temperature, then the thermal conductivity of the PCB (its substrate and metal traces), the package materials, and the die itself are all very well characterized. You know the overall power dissipation, and can calculate results for various assumptions which should be reasonably accurate.
Another way is to use an IR camera and take a thermograph of the top of the package. The most simplistic result would be found under the assumption that the package is "thin" compared to its width and length, and that the temperature is uniform in the plane of the surface, then you can assume that its just an infinite sheet which means the edges don't contribute. In short, you assume the temperature at the center is the temperature of the whole thing. Since the thickness of the package and the thermal conductivity of the material are known, you can apply the heat equation and find the die temperature (under the assumption that the die is of uniform temperature and thus there actually exists a single "die temperature") An improvement in the result can possibly be made by also considering the thermal conductivity of the interface between the die and the package.
Typical thermal imagers (without cryogenic cooling) have accuracies in the ballpark of 2C and sensitivities of around 80mk. The thermograph should be able to give you a reasonable idea of whether that simplistic set of assumptions is reasonable. The temperature should be relatively uniform except at the edges, for suitable hand-wavy definitions of center, edge and uniform.
You might be able to improve the calibration of the instrument, perhaps even approaching the sensitivity (the minimum temperature difference it can see) by comparing the device under test, with a sample that you can directly control the temperature of. In other words, if the camera, under conditions of the same ambient temperature,is used to image a device that is being heated to a known temperature, its thermograph , can be compared with the thermograph of the DUT. When the known temperature is adjusted so that the thermograph shows the same as the DUT, then that's your die temperature within the error of your ability to control (and know) the temperature, and the thermal sensitivity of the camera (give or take)
The other way to attempt to improve the result is to improve the model. Take into account the pins and edges and bottom,and assume a nonuniform die temperature,in all three dimensions. However, that violates the assumption that the die temperature is a single number which is what was initially asked for and instead calculates a temperature field over its volume. One exception might be assuming the die has a temperature gradient across its thickness, and (while still using the assumption of infinite width and heigh) and using in addition to the original parameters, the thermal conductivity of the silicon wafer, solving for the surface temperature of the die. (Change the definition of die temperature to die surface temperature)
The first ideal is to be able to measure temp inside the P2 itself - yes, that is only one location on the die.
External PCB temperature is easy, and simple enough with the devices already listed - small i2c temp sensors.
An i2c device could be reverse-side centre mounted, right where the hand assembly solder-access hole is currently located, but that bumps to 2-sided assembly, which I have in the less-ideal basket at the moment.
If caps on the reverse side are found to be measurably better, than on the top side, maybe double-side assembly will be more common ?
Back to on-die sense : the on-die candidates are a reverse diode, and/or Current/resistor combination tracking.
LFOSC is also possible, but that needs external-part help, and worse, requires that SysCLK is radically changed during temperature capture.
It would be nice to see some diode millivolts table, read with a multimeter (drive any IP pin negative), on a real P2 device warmed/cooled.
There is an air gap there. The die is in contact with the package, but there are also losses to the outside air too.
Over a sustained time, more consistent heat profile, the top temp will be closely related to the die temp, and not too much different.
What won't get seen is a spike, for example.
-Phil
ESD/Substrate clamp diodes - 1k Ohms measured 416mV, so diode inject current is ~416uA, for this meter. NXP HCT573 : TI HCT573 NXP 40106 Prop1.IO Vdd : 570mV 556mV 608mV OP : 647mV 636mV 670mV 416mV IP : 744mV 698mV 820mV Hot-test TI 573, OP diode 636mV -> 550mV heatedLooks to be large variation across process, less across same-process/different vendor.IP clamp is weaker than OP clamp, because the NMOS Drive structure is missing, just ESD clamps are present.
Very consistent within a device, with 1-2mV variations btween like-pins.
Probably, but that's not really a run-time solution .... and you have disturbed the cooling significantly in your test.
Someone may want to top-mount a heatsink, as seen commonly in RaspPi / NanoPi cooling solutions.
But if you get a good reading of the temp at the center of the package, you can calculate the die temperature from that because everything you need to do that is fairly well defined.
The ADC pins have an internal calibration ability where they connect their input to Gio (ground) or Vio, independent of externally connected circuitry. If you average these two values you'll get a range of values varying by pin, in one test I saw a range of 31657 through 34354 at room temperature
The pins whose average is 'low' - down the 31657 end - seem to have a stronger positive temperature coefficient than those in middle to upper ranking. So these pin(s) could be used to gauge temperature.
While the exact pins used may vary from device to device, ranking them may provide us a way forward.
Its likely some calibration data would need to be stored with the device, at least until we've run a few production batches and seen the variation from batch to batch. However at least we have something internal that responds to temperature change.
The attached plot has ranked pins by their warm average (red curve, room temp 22 C, plus chip self heating).
The blue waveform is same module on dry ice (surface about -28 C). So the range is pretty extreme 50 K / 90 F
Certainly an interesting approach, but I suspect that rule could vary from part to part, and the noise-levels here look high.
An appeal of this tho, is it is a almost pin-less sense - there is no IO connection, but you do need to flip the pin-mode to extract the ADC info.
Did you try Current-source/sink, driving internal Resistors voltage readings for temperature effects ?
It does look like the ADC Span is ok to read the clamp diodes, from your other postings, but that needs a means to bias the diode.
A quick test could be a multimeter on diode-range, DC biasing the IO diode and reporting mV, whilst P2 reports counts ?
I was focusing on -ve diode, to allow TEST pin to be used, but maybe +ve IO diode is also a candidate, as many system have 5V rails, so injecting a modest + current might actually be simpler into +ve diode ?
Addit: there is appeal to use a somewhat dedicated pin for temperature, and from my readings above, the CMOS IP pins have softer clamps than IO drive pins, so it might be that IP pins on the FLASH memory, are soft enough to not disturb the IO diodes on P2.
If you do get a chance to run a multimeter diode-range DC test, checking the FLASH pins vs not-connected-at-all pins, could reveal if the connected flash affects things.
At the hot end, the P2 drop will be many mV lower anyway, so that effect will be less as the P2 heats up.
Where it might disturb things, is on the active-cooling uses, where P2 temp could be lower than Flash.
The advantage of the technique I outlined before would be, if it works, its fully internal
That alone would be super useful.
Perhaps we don't want to eliminate the pullup on P59, after all : )
Jonathan
The limitter on the PLL is not the VCO, but the 10-bit VCO divider. It seems to top out at around 410MHz.
Following this line of thought, & looking at the plots here
https://forums.parallax.com/discussion/comment/1450046/#Comment_1450046
Is this showing the same effect - lower-left pins have a much larger dX with MHz (die temp?) than upper right pins ?
The good news, is all plots in those outer regions, have similar shapes to nearby plots.
If true, that indicates you need to search and find suitable LL/UR pin sets, and there might be enough signal in that noise to derive temperature ?
Ozprop likely did those tests in time sequence with MHz increasing, so his chip was continuously getting hotter and hotter.
What might be interesting to test is to test ADC at 300MHz and hit it with freeze spray and see if what we're seeing is being driven primarily by temperature, rather than say capacitive parasitics.
.. and that pesky 320MHz ..