@cgracey said:
Here is a 2-cog, 128K-hub, 32-pin version that would fit into the Amkor 7x7mm 48-pin package:
What is the chance of this seeing the light of day?
Well, fab capacity is sold out through next year and we'd have to spend maybe $300k to make it happen. We probably won't be able to do this for a while, yet.
Does this mean Parallax couldn't get any more P2's until 2025?
I know, the reduced P2 version won't happen anytime soon, if at all. So just for the records...
I think that 3 cogs is the minimum to make some useful application. Tecnically, you can do a lot with only two P2 cogs. But this means you have to hand-optimize the code very carefully and use interrupts.
The typical application has some sort of main loop which handles user input and is written in Spin or C. High-level languages and interrupts do not mix very well. Then you need at least two extra cogs to handle local IO (ADCs DACs, sensors etc.) and communication (serial, network...). The restriction of having only two cogs would mean you can't use standard driver software to handle interfaces but instead have to hand-code everything and pack two different tasks into one cog.
I have only one application that would run on a 2-cog P2: The Goertzel capacitive encoder. It uses one cog for the encoder input and another for the QPSK modulated communication with the servo controller. But I definitely need the CORDIC to decode the angle of the encoder derived from the Goertzel ADC inputs and to encode/decode the QPSK signals. So no CORDIC, no fun.
For me the biggest downside of the P2 is the size.
I would love to see a 4-cog 16-smart pins 128K ram version in as small a package as possible.
Just my two cents...
Bean
TSMC is trying to encourage everyone to move everything larger down to 28 nm and make that the base for all planar (pre-FinFET) processes moving forward. I wonder if they are offering the same setup costs as 180 nm though.
@pik33 said:
It is 180 nm. Reducing this can make the package smaller even with 16 cogs and 1 MB.
I don't know what I would do with 16cogs, but 2MB of memory would allow for emulation for an Amiga 1200...since we're dreaming.
@evanh said:
TSMC is trying to encourage everyone to move everything larger down to 28 nm and make that the base for all planar (pre-FinFET) processes moving forward. I wonder if they are offering the same setup costs as 180 nm though.
the RP2040 in the Pico is 40nm, reportedly
28nm would be really sweet! Maybe do the P3 in that, and have FloatingPoint cogs for the 8 cogs in addition to 8 current cogs. Oh, the possibilities...
What are those discussion good for if not for infinite growth of frustration? We ask to have what we will not get in the near future and can not reach with what we have now that what we easily reached when we dreamed to have, what we have now and what still creates new wishes!
Dreaming of things to come has driven exploration for a long time. Weren't you around when the P2 came together?
I agree also that the current P2 has not been fully explored either. So creativity can be expressed in software on the current P2 as well.
Comments
Does this mean Parallax couldn't get any more P2's until 2025?
Luckily Parallax was kept in-the-loop, and has made some eye-wateringly huge orders and reservations to ensure stock keeps flowing.
I know, the reduced P2 version won't happen anytime soon, if at all. So just for the records...
I think that 3 cogs is the minimum to make some useful application. Tecnically, you can do a lot with only two P2 cogs. But this means you have to hand-optimize the code very carefully and use interrupts.
The typical application has some sort of main loop which handles user input and is written in Spin or C. High-level languages and interrupts do not mix very well. Then you need at least two extra cogs to handle local IO (ADCs DACs, sensors etc.) and communication (serial, network...). The restriction of having only two cogs would mean you can't use standard driver software to handle interfaces but instead have to hand-code everything and pack two different tasks into one cog.
I have only one application that would run on a 2-cog P2: The Goertzel capacitive encoder. It uses one cog for the encoder input and another for the QPSK modulated communication with the servo controller. But I definitely need the CORDIC to decode the angle of the encoder derived from the Goertzel ADC inputs and to encode/decode the QPSK signals. So no CORDIC, no fun.
For me the biggest downside of the P2 is the size.
I would love to see a 4-cog 16-smart pins 128K ram version in as small a package as possible.
Just my two cents...
Bean
It is 180 nm. Reducing this can make the package smaller even with 16 cogs and 1 MB.
TSMC is trying to encourage everyone to move everything larger down to 28 nm and make that the base for all planar (pre-FinFET) processes moving forward. I wonder if they are offering the same setup costs as 180 nm though.
I don't know what I would do with 16cogs, but 2MB of memory would allow for emulation for an Amiga 1200...since we're dreaming.
the RP2040 in the Pico is 40nm, reportedly
28nm would be really sweet! Maybe do the P3 in that, and have FloatingPoint cogs for the 8 cogs in addition to 8 current cogs. Oh, the possibilities...
What are those discussion good for if not for infinite growth of frustration? We ask to have what we will not get in the near future and can not reach with what we have now that what we easily reached when we dreamed to have, what we have now and what still creates new wishes!
Dreaming of things to come has driven exploration for a long time. Weren't you around when the P2 came together?
I agree also that the current P2 has not been fully explored either. So creativity can be expressed in software on the current P2 as well.