Fozzie on a pin
ozpropdev
Posts: 2,792
Hi All
I finally woke fozzie up again and he's spinning nicely on the P2 silicon.
This code really works the hub and cordic and uses all 8 cogs.
With no additional components we have NTSC output on a IO pin. Very Cool! :cool:
Two versions Big and little fozzie.
I finally woke fozzie up again and he's spinning nicely on the P2 silicon.
This code really works the hub and cordic and uses all 8 cogs.
With no additional components we have NTSC output on a IO pin. Very Cool! :cool:
Two versions Big and little fozzie.
Comments
Will have to wait till I am on my pc
Couldn't resist. I just had to go take a look on my pc. Nice job Brian. Had a quick once over on the code but forgot to check the resolution
Same on My iPad, had to revert to my win laptop.
Jim
That should be the case.
It's a shame that the modulator got messed up. It was like icing on the cake.
At least we can do lots of testing and give the chip a good workout.
Chip,
are the ~1500 chips being packaged and if so when do you expect them?
With these, there's no immediate hurry for a silicon respin.
Here's a more desktop friendly view that's a smaller filesize to boot:
I will use that in the future.
It's good that Chip requested MP4 to be added to the forum recently.
Part of trick of making the filesize smaller without sacrificing quality was to strip out the audio track. That was taking about 2 MB I think.
I guess I've been given moderator power because I can click "edit" on anyone's post and see the source.
I ran fozzie at 340MHz and it worked! Cordic and hub spinning nicely.
5 volt supply showed 550mA current.
Fozzie was spinning so fast I was worried the pixels might fly of the screen
Wow!
I'm kind of leaning towards NOT putting clock gating in, because it would only drop peak performance. If anything, maybe we should see if we could push to an official 200MHz rating.
That sounds maybe too spartan ? - and perhaps that is why ozpropdev is able to report 340MHz ? (on what I presume is a fully populated PCB )
A gate there just delays the SysCLK, but does not add into the Tsu,Th budgets (apart from maybe some small clock skew allowances)
Do you know exactly where the tools place these automated 'clock gates' and how much do they save ?
So all we can really measure is the 5v current, but that still tells a fair bit.
So, are you getting 340MHz from 1.8V, then?
I know my setup is loosey-goosey.
I remember hearing about a setting in the tools where you tell it at what threshold number of flops to implement a common clock gate at. I think 4 flops was kind of a minimum.
I don't know how high up the clock tree automated decisions are made on clock-gating. We will be asking about it.
There's a couple of minor artifacts but everything is clearly recognisable
Current consumption is about 16mA when running (keep in mind this has 8 cogs going, too), including the video load
This P2 chip has quite a 'range'...
That's great news. I saw artifacts at 10MHz, but they went away at 12.5MHz. At 8 MHz, your timing granularity is a big 125ns, which is pretty chunky. At 340MHz, it drops to 2.94ns, which is really fine.
My testing today showed that setup and hold timing on the DAC data is apparently A-okay, from one end of the speed/voltage extreme to the other. I think the chip design tools these days are really thorough.
You really should add some more caps... that's a quite abnormal test set-up.
Add them in stages and record the MHz changes as you go ?
Lowest clock rate: 7.16129 MHz - 12mA at 5v, 1 minion cog
Highest clock rate: 348 MHz - 540 mA at 5v, 4 minion cogs
We tried several different divisors for 348 MHz, a lot of weird stuff happens at the step immediately afterwards (eg 350 MHz has 'half a fozzie') etc.