Here is the code. Note that the PLL is using the biggest XI divide possible (64) and a big VCO divide of 512, with a post-VCO divide of 2. This results in 20MHz / 64 * 512 / 2 = 80MHz, but with the slowest/weakest PLL feedback possible, and the image shows no jitter, at all:
Did you see jitter at other settings ? With an Analog VCO, it should not matter too much where Fpfd is set ?
There seems to be some problem with the IQ modulator in the colorspace converter. I'm looking at it, trying to see if maybe the ASIC synthesizer might have done something different than the FPGA synthesizer.
Here is the code. Note that the PLL is using the biggest XI divide possible (64) and a big VCO divide of 512, with a post-VCO divide of 2. This results in 20MHz / 64 * 512 / 2 = 80MHz, but with the slowest/weakest PLL feedback possible, and the image shows no jitter, at all:
Did you see jitter at other settings ? With an Analog VCO, it should not matter too much where Fpfd is set ?
I saw some wavy jitter when I did the same setting, but with the VCO divider set to 1024 and a post-VCO divider of 4. This meant that the VCO was running at 320MHz, which is way beyond where it was designed to go. I made it run safely up to 250 MHz, worst case.
There's definitely something wrong with the IQ modulator in the colorspace converter. I was using "$signed(<term>)" to sign-extend some values to add to other values which already had the full number of bits, but there seems to be a problem coming from these sections. I've asked Wendy to look at it.
Are the multipliers in the colorspace converter also close to the critical path, like the cog MUL instructions?
That's what is hard to get through people's heads. Maybe 1/4 of all paths are "critical", in the sense that they were optimized up to the goal line and no further. So, the whole chip fails at the same frequency, but that frequency is maybe 280MHz for this batch of chips, running at room temperature.
In the case of this IQ modulator, it is a logic problem.
Are the multipliers in the colorspace converter also close to the critical path, like the cog MUL instructions?
That's what is hard to get through people's heads. Maybe 1/4 of all paths are "critical", in the sense that they were optimized up to the goal line and no further. So, the whole chip fails at the same frequency, but that frequency is maybe 280MHz for this batch of chips, running at room temperature.
In the case of this IQ modulator, it is a logic problem.
Is there a workaround or does this require a spin?
Uh Oh,
I hope this doesn't mean a respin and extra cost to you? Is this all with the same chip? Perhaps try the same test on another one?
I tried the IQ modulator in cog1 and it does the same thing as the one in cog0. I know that the problem is that the ASIC compiler interpreted the Verilog source code a little bit differently than the FPGA compiler had been. This is a very subtle thing that I never thought to request a silicon simulation of.
Are the multipliers in the colorspace converter also close to the critical path, like the cog MUL instructions?
That's what is hard to get through people's heads. Maybe 1/4 of all paths are "critical", in the sense that they were optimized up to the goal line and no further. So, the whole chip fails at the same frequency, but that frequency is maybe 280MHz for this batch of chips, running at room temperature.
In the case of this IQ modulator, it is a logic problem.
Is there a workaround or does this require a spin?
A respin.
The chip we have seems to do everything else, though.
I still need to dig into why the P59 resistor is required.
There's definitely something wrong with the IQ modulator in the colorspace converter. I was using "$signed(<term>)" to sign-extend some values to add to other values which already had the full number of bits, but there seems to be a problem coming from these sections.
We have been using a similar approach, but only for simulation. Synthesis to asic gets a specific "function" so to say, the target is also a 180 nm process.
The reason all timing paths are optimized to the point of the goal line, and no further, is because to push any path beyond the goal line only steals routing and placement resources which some other path is going to need in order to reach the goal line. You tell the compiler to jump, it asks, "How high?", and makes it happen without any excess. It's kind of like not over paying your bills, or something.
Are the multipliers in the colorspace converter also close to the critical path, like the cog MUL instructions?
That's what is hard to get through people's heads. Maybe 1/4 of all paths are "critical", in the sense that they were optimized up to the goal line and no further. So, the whole chip fails at the same frequency, but that frequency is maybe 280MHz for this batch of chips, running at room temperature.
In the case of this IQ modulator, it is a logic problem.
Is there a workaround or does this require a spin?
A respin.
The chip we have seems to do everything else, though.
I still need to dig into why the P59 resistor is required.
If that's the only problem it's not that bad. I suppose people will want NTSC video though. However, I'm perfectly happy to have a chip that can't do it!
I tried the IQ modulator in cog1 and it does the same thing as the one in cog0. I know that the problem is that the ASIC compiler interpreted the Verilog source code a little bit differently than the FPGA compiler had been. This is a very subtle thing that I never thought to request a silicon simulation of.
Are there any means for you to get a schematic diagram, up to the gate level, from both (Asic compiler x Fpga compiler) interpreted versions of that exact part of the circuit, in order to compare them and be sure of the exact extent of their differerences?
If that's the only problem it's not that bad. I suppose people will want NTSC video though. However, I'm perfectly happy to have a chip that can't do it!
This modulator is useful for generating baseband video, but also it can be used for FM, AM, and PSK signalling.
When the problem is understood, exactly, I'll go through the rest of the Verilog and make sure we don't have any other of these instances.
We can get the current chip out to customers, then follow up a few months later with an improved version with a working modulator and maybe lower power.
Wendy said that in order to meet the speed goal, she used a bunch of compiler switches that might have disabled true clock gating. That's why the frequency/power profile looks like like that of an FPGA.
I supose that all the flip-flops used are from the master-slave type, but, even then, the first stage gates would suffer from severe switching noise, by having their inputs constantly changing, albeyt the changes don't make it into the second stage, unless their clock has some slow-ramping behaviour.
With those many thousands of synchronizers, being furiously hammered at their input stages, some excess current consumption was no surpise at all.
This modulator is useful for generating baseband video, but also it can be used for FM, AM, and PSK signalling.
Also component, useful on a ton of displays.
We should make a test suite. Subtle things like this may be lurking.
I didn't mean it should never be fixed. I just meant that I would find a P2 with that particular bug still useful for the sorts of testing I want to do.
We can get the current chip out to customers, then follow up a few months later with an improved version with a working modulator and maybe lower power.
While I don't share Yanomani and David's disdain for NTSC, I am very happy with the course of action you've indicated here. The biggest tragedy would be to decide not to release this version of the chip to ANYONE because a few things could be improved upon.
While I don't share Yanomani and David's disdain for NTSC, I am very happy with the course of action you've indicated here. The biggest tragedy would be to decide not to release this version of the chip to ANYONE because a few things could be improved upon.
Hello K2
Please, don't get me wrong, I'm not "disdaining" NTSC, nor anything else. Far from me doing so!
I am in full agreement with David Betz, because, as he stated, "I'm perfectly happy to have a chip that can't do it!", since I don't need, and in fact, I can't use a NTSC signal to display anything in my shack-lab.
I only have two ancient VGA wichever monitors to work with: the one in my front being a venerable Samsung SyncMaster 794MBplus, aka "the TUBErculous", and the other, another piece of relicary art, a LG FLATRON L1530S, the "SCAR-SMASHED face". Don't even ask what they are capable for; I always agree to watch wichever image they intend to present to my eyes. I'm a no-complainer, at all!
Here at our home, there is a single TV set, at the living room, and I can't even imagine my actual (and seventh) wife, giving me a single chance to use it for any experiment or any other "unintended use" (from her perspective, to be clear), in detriment of HER time in front of it, be it for watching the news channels or her prefered soap opera, or even as an ambient sound generator of wichever noise, for she to take her naps, whenever she wants to.
Thus, I know democracy as a thing that exists (and persists) only outdoors; indoors were, are and sure will be a Gulag, forever...
We can get the current chip out to customers, then follow up a few months later with an improved version with a working modulator and maybe lower power.
While I don't share Yanomani and David's disdain for NTSC, I am very happy with the course of action you've indicated here. The biggest tragedy would be to decide not to release this version of the chip to ANYONE because a few things could be improved upon.
I don't have a distain for NTSC. I'd just rather get a P2 chip *now* without it than wait another many months to get a fixed one with it. I like Chip's idea of getting the current chip out and following up with an improved version later.
David, I did not mean to suggest you did have disdain. I was just adding to the list of modulator uses. That is a cool feature beyond NTSC.
I am all for running what we got right now. If nothing else, we get tools and testing done.
The logic difference could present elsewhere too. Many eyes is the right move. Hopefully, the modulator is an edge case.
There is a ton all of us can do too. Finally, we can be doing it on real silicon! I am sure the, hopefully few issues will get bundled up into an equally hopefully minor rev, and its done.
A ROM revise is a bonus. I actually think that may pay off very well. What we got is excellent, but was rushed.
Chip, Parallax has this right. Run 'em.
Onward from here. We all are going to be on a get our visions done, and report mission. I think it is amazing to see just how much came through with out a glitch!
At this VDD current level, I'm dropping ~200mV just over the wires going to the board, so I need to output 2.00V to get 1.80V onto the board.
Did you check the drop across the board, to the P2's pins ?
A switching regulator can take the voltage feedback from the P2 pins, but you still want the core ring to have least voltage drop.
Are the multipliers in the colorspace converter also close to the critical path, like the cog MUL instructions?
That's what is hard to get through people's heads. Maybe 1/4 of all paths are "critical", in the sense that they were optimized up to the goal line and no further. So, the whole chip fails at the same frequency, but that frequency is maybe 280MHz for this batch of chips, running at room temperature.
In the case of this IQ modulator, it is a logic problem.
Is there a workaround or does this require a spin?
A respin.
The chip we have seems to do everything else, though.
I still need to dig into why the P59 resistor is required.
If that's the only problem it's not that bad. I suppose people will want NTSC video though. However, I'm perfectly happy to have a chip that can't do it!
Same here. Minimum video resolution I want is 640 x 480.
Comments
Did you see jitter at other settings ? With an Analog VCO, it should not matter too much where Fpfd is set ?
I saw some wavy jitter when I did the same setting, but with the VCO divider set to 1024 and a post-VCO divider of 4. This meant that the VCO was running at 320MHz, which is way beyond where it was designed to go. I made it run safely up to 250 MHz, worst case.
I'm having trouble with NTSC, as the colorspace converter's IQ modulator is not working right.
As for VGA, all 5 pins (4 are DACs) consume 14mA of VIO current, all together.
I hope this doesn't mean a respin and extra cost to you? Is this all with the same chip? Perhaps try the same test on another one?
That's what is hard to get through people's heads. Maybe 1/4 of all paths are "critical", in the sense that they were optimized up to the goal line and no further. So, the whole chip fails at the same frequency, but that frequency is maybe 280MHz for this batch of chips, running at room temperature.
In the case of this IQ modulator, it is a logic problem.
I tried the IQ modulator in cog1 and it does the same thing as the one in cog0. I know that the problem is that the ASIC compiler interpreted the Verilog source code a little bit differently than the FPGA compiler had been. This is a very subtle thing that I never thought to request a silicon simulation of.
A respin.
The chip we have seems to do everything else, though.
I still need to dig into why the P59 resistor is required.
We have been using a similar approach, but only for simulation. Synthesis to asic gets a specific "function" so to say, the target is also a 180 nm process.
Fix at mask level perhaps? Like the ROM?
Are there any means for you to get a schematic diagram, up to the gate level, from both (Asic compiler x Fpga compiler) interpreted versions of that exact part of the circuit, in order to compare them and be sure of the exact extent of their differerences?
Thousand times 100%, I totaly agree with you!
This modulator is useful for generating baseband video, but also it can be used for FM, AM, and PSK signalling.
When the problem is understood, exactly, I'll go through the rest of the Verilog and make sure we don't have any other of these instances.
We can get the current chip out to customers, then follow up a few months later with an improved version with a working modulator and maybe lower power.
Wendy said that in order to meet the speed goal, she used a bunch of compiler switches that might have disabled true clock gating. That's why the frequency/power profile looks like like that of an FPGA.
https://forums.parallax.com/discussion/comment/1446971/#Comment_1446971
I supose that all the flip-flops used are from the master-slave type, but, even then, the first stage gates would suffer from severe switching noise, by having their inputs constantly changing, albeyt the changes don't make it into the second stage, unless their clock has some slow-ramping behaviour.
With those many thousands of synchronizers, being furiously hammered at their input stages, some excess current consumption was no surpise at all.
Also component, useful on a ton of displays.
We should make a test suite. Subtle things like this may be lurking.
Hello K2
Please, don't get me wrong, I'm not "disdaining" NTSC, nor anything else. Far from me doing so!
I am in full agreement with David Betz, because, as he stated, "I'm perfectly happy to have a chip that can't do it!", since I don't need, and in fact, I can't use a NTSC signal to display anything in my shack-lab.
I only have two ancient VGA wichever monitors to work with: the one in my front being a venerable Samsung SyncMaster 794MBplus, aka "the TUBErculous", and the other, another piece of relicary art, a LG FLATRON L1530S, the "SCAR-SMASHED face". Don't even ask what they are capable for; I always agree to watch wichever image they intend to present to my eyes. I'm a no-complainer, at all!
Here at our home, there is a single TV set, at the living room, and I can't even imagine my actual (and seventh) wife, giving me a single chance to use it for any experiment or any other "unintended use" (from her perspective, to be clear), in detriment of HER time in front of it, be it for watching the news channels or her prefered soap opera, or even as an ambient sound generator of wichever noise, for she to take her naps, whenever she wants to.
Thus, I know democracy as a thing that exists (and persists) only outdoors; indoors were, are and sure will be a Gulag, forever...
Henrique
I am all for running what we got right now. If nothing else, we get tools and testing done.
The logic difference could present elsewhere too. Many eyes is the right move. Hopefully, the modulator is an edge case.
There is a ton all of us can do too. Finally, we can be doing it on real silicon! I am sure the, hopefully few issues will get bundled up into an equally hopefully minor rev, and its done.
A ROM revise is a bonus. I actually think that may pay off very well. What we got is excellent, but was rushed.
Chip, Parallax has this right. Run 'em.
Onward from here. We all are going to be on a get our visions done, and report mission. I think it is amazing to see just how much came through with out a glitch!
Did you check the drop across the board, to the P2's pins ?
A switching regulator can take the voltage feedback from the P2 pins, but you still want the core ring to have least voltage drop.
Same here. Minimum video resolution I want is 640 x 480.