Was browsing the P2 documentation today trying to figure out if/how the streamer might be able to support parallel video busses of LCD panels.
Maybe these are going be questions where only Chip currently knows the answers unless someone's already done something like this on one of the P2 FPGA platforms:
For an LCD can you get its CLK and DE signal output synchronously with the video data and in the appropriate phase with the streamer or smartpins perhaps? Let's say the LCD panel needs 40MHz which is a nice submultiple of some 160MHz system clock for example. Will it be possible to have these two LCD control signals generated correctly by the COG or other internal HW and output to the LCD panel?
Also if an LCD with say 18 parallel video inputs (6bpp x 3 RGB) is used, can the unused RGB data bit pins (the LSBs) of the 8:8:8:0 formatted output the streamer generates be freely allocated to other COGs/functions, also in particular including their use for CLK and DE signals as mentioned above, or are there some other limitations there?