Final P2 Power Estimation
cgracey
Posts: 14,155
We had a chance to run some more simulations, so I thought a little more about the test program that tries to maximize power consumption.
I had eight cogs executing from register memory at 180MHz. I made their loops in hub memory, instead, which forces frequent FIFO reloads. The simulation showed a worst-case power consumption of:
2.4 Watts
That measurement was taken at fastest process corner, highest voltage (1.98V) and lowest temperature (-40C). I don't think a customer will ever see more than 2 Watts consumed by the core. So, the original estimation of about 2 Watts is probably accurate.
I had eight cogs executing from register memory at 180MHz. I made their loops in hub memory, instead, which forces frequent FIFO reloads. The simulation showed a worst-case power consumption of:
2.4 Watts
That measurement was taken at fastest process corner, highest voltage (1.98V) and lowest temperature (-40C). I don't think a customer will ever see more than 2 Watts consumed by the core. So, the original estimation of about 2 Watts is probably accurate.
Comments
I knew hubexec would push the power envelope, and we are likely to see a lot of hubexec cogs in P2.
However, in reality, I doubt any customer is going to get anywhere near 2W. Most will be hard pressed to even see 1W.
The DAC burns constant power. The ADC burns about 1.5mA. Swinging the output at high frequency will take power, too
Are there any 'damage' paths ? - eg 3v3=3v3 with 1.8V = 0, or 3v3=0 and 1.8V = 1.8V ?
With the 3v3 elements resetting at the same time, provided the core is up before reset is released, things should be ok ?
Of course there may be more suitable devices, just happened to find this one and start looking at it and wondering what the P2 requirements would be there with its voltage rails.
ON Semiconductor have a 1Amp one for 24cent: NCP59800 (nice big 0.65mm pad pitch and top layer thermal spread)
https://www.mouser.com/ProductDetail/ON-Semiconductor/NCP59800BMNADJTBG?qs=/ha2pyFadujw87dMGaQs86X4pq3J/8Ei9C2UMd/G2yhz6CoIN/zrhlNiA2PNN/Ks
Use two, one for 3.3v and one for 1.8V and use the soft start feature and tie the 1.8V output to enable pin on the 3.3V,
as enable have 1.2v threshold, could resistor divide it down to 1.7V threshold if you want it to wait just a little longer
Or the 1.8V ldo's enable pin tied to the 3.3V output if power up sequence is opposite.
1.8v core voltage should definitely be direct switcher supplied though. And this will control just as easily, btw. All sequencing can be downstream of the 1.8v supply. Otherwise you're talking a 3-4 volt linear drop to the 1.8 volts - the losses aren't pretty.
Agree, if the P2 draws up to 1A on its 1.8V under heavy load then this is an additional 3-4W of loss that way which is already a lot more than the P2 itself requires. A switching regulator for the 1.8V and a 3.3V linear LDO regulator from (say) a 5V rail when enabled by the 1.8V core output though sounds like a reasonable compromise in heat wasted and the hopefully reduced analog noise it delivers. I am going to consider that approach now as I have an potential application where I'd need 5V (for LCD backlighting, audio amp, and a USB host) and 3.3V and 1.8V for the P2, all from a single higher supply from 6-12V. This type of switcher and another 3.3V LDO might work, though I don't like the idea of needing to go design and analyze phase margins and gain response to see if it will be stable etc, as I'd then have to try to remember all that control theory stuff from my earlier EE days. LOL.
By the way this topic may have ramifications for Peter Jakacki's P2D2 board if the 3.3V P2 supply has to come up only after the 1.8V, though that discussion probably belongs in his thread.
https://www.mouser.com/Semiconductors/Power-Management-ICs/Voltage-Regulators-Voltage-Controllers/Switching-Voltage-Regulators/_/N-668jtZ1yzvvqx?P=1z0wa91Z1z0wcpvZ1z0vksyZ1z0wadvZ1z0w6coZ1z0wbyrZ1z0w25cZ1z0wd5e&Ns=Pricing|0
Does the P2 have two 1.8V Vcore inputs?, simplest would be 2 of these dc-dc with built-in inductor. (though end of life, 9000 is on order)
https://www.mouser.com/ProductDetail/Murata-Electronics/LXDC2HL18A-052?qs=sGAEpiMZZMsc0tfZmXiUnTpKkCM1UEbNMi/WfCHYhoo=
https://www.digikey.com/product-detail/en/murata-electronics-north-america/LXDC2HL18A-052/490-5791-1-ND/2783646 got them in stock
Or a single 1.5A
https://www.mouser.com/ProductDetail/Murata-Electronics/LXDC2XQ18A-253?qs=/ha2pyFadujKXlMxLQJm3aZ3zvItRb4vZqrrRY6/Qo4wSndokpJKtQ==
The Torex range looks like the way to go for something similar.
Yes, but you do pay a premium for the merged packaging, and that also puts more power loss into a small area.
You can get Dual 3v3/1v8 fixed-voltage switching regulators, like PAM2306AYPKE IC REG BCK 1.8V/3.3V 1A DL 12DFN 0.27550/3k
I like the idea of an i2c programmable regulator, but it's not easy finding one that is mainstream, and not a silly price.
It may be cheaper to use a 25c MCU with i2c/PWM peripherals, and control standard FB regulators from that ?
Or, you can take the KISS path, and get a simple, high volume part like AP3402 TSOT23-6 2A at 12c/3k - the AP3402 includes a Power Good & Enable
Addit: the FP6373 looks pin compatible with AP3402, but 3A nominal, and 9.16c/500
For designs that do not need the full power envelope, simple LDOs like SOT223 1.2A LDL1117S18R / LDL1117S33R have real appeal. ( the price of $0.0890/2k5 helps too )
Looking around for more top-end Power solutions, for lab testing and characterization uses, I find the MxL7704-A / MxL7704-X as used in the latest RaspPi
This could pair with the new Microchip PAC1932/PAC1933 Current/Voltage Monitor.
2 part codes with differing default settings,
MxL7704-A is ARM/Pi sequencing, 1.8V up after 3v3 _/=, down before 3v3 =\_
MxL7704-X is Xilinx sequencing, 1.8V up before 3v3 _/=, down after 3v3 =\_
Maybe both can be tested ? -
Input voltage range: 4.0V to 5.5V
4 Synchronous Buck Regulators
Internally compensated current mode
1MHz to 2.1MHz switching frequency
Buck 1: 3.0V to 3.6V, 20mV step, 1.5A
Buck 2: 1.3V to 1.92V, 20mV step, 1.5A
Buck 3: 0.8V to 1.6V, 6.25mV step, 2.5A
Buck 4: 0.6V to 1.4V, 6.25mV step, 4A
100mA LDO: 1.5V to 3.6V, 20mV step
±2% maximum total dc output error over line, load and temperature
3.3V/5V 400kHz I2C interface
Dynamic voltage scaling
Status monitoring by channel
Sequencing control
Input voltage status register
Highly flexible conditional sequencing engine with external input
2 configurable PGOOD outputs
Adjustable switching frequency
5mm x 5mm 32-pin QFN package
If anyone wanted to push P2 below 1.3V, then Buck3 could be used ?
Looks to be ~ $2.30/3k (I'm sure RaspPi buy them for much less ! ) so not low-end, but it is compact and highly flexible, and being able to readily adjust voltages over i2c, is good for data-sheet generate.
( They do not seem to do a cheaper one, with fewer converters.)
P2D2 has an LDO footprint in parallel with the switcher, all I would do is use a 1.7V LDO there and since the processor is going through reset and running RCFAST on one cog the actual power consumption is very small, especially since we are only talking about milliseconds anyway.
It's not clear on P2 how the Reset/registers span the voltage domains, or if there are any damage paths, or how critical sequencing is.
Clearly, you want to avoided device damage, and avoid undefined pin states.
Xilinx version of that MxL7704 seems to bring up the core, I guess to configure things and define IO settings, before VIO applies, whilst -A version brings up VIO, and seems to rely on (reset) IO registers giving defined states, before the core is applied.
With Power-Good outputs, the P2 should be held in (async?) reset .
The lowest cost parts I linked above, with PG, release on 90% of Nominal, and have soft-starts of 1~2ms
Wow things must be getting bad if we need to resort to use a motor controller IC to power the P2! LOL.
Yes, this whole matter of powering the P2 could become over complicated quite easily yet simultaneous powerup is dead simple.
Hehe, no, not that bad that it needs kW power handling
The appeal is being able to easily control the voltages, mainly on a well featured EvalPCB, so the MxL7704 is one candidate.
The new Microchip PAC1932 series can read I.V to good 16b precision, at under $1
One irony is, that specific purpose MxL7704 part is actually not super-cheap, at $2.30/3k ( but it is powerful, and keeps BOM small, and appears to have natural range limiting )
An alternative would be a MCU with a clean/decent 2+ DAC like EFM8BB31F16G-B-QFN24R 24QFN $0.62370/3k plus 2 mainstream SOT23-6 SMPS parts, ( FP6373 ~ 9c or AP3402 ~ 12c), for a sub $1 BOM
An EFM8BB3 can drive Vo adjustments to either Linear or PWM-FB regulators, and could read 12b ADC, with an external dual-current amplifier.
The EFM8BB31F64 has 4 x 12b DAC, ( ~$1) so that could support both Voltage adjust, and P2 ADC checking.
I will want to use the smartpins in ADC and DAC mode, but I'll need to couple them to op amps to boost the level to around +-10V.
As I understand it, without LDO on the +3.3V VXXXX pins, ripple will interfere with the accuracy of these modes. Do we have any anecdotal indicators on "how much" yet?. Should I just go ahead and assume every VXXXX group will need LDO for reasonable operation? I'm still quite a newbie, so this still feels very hand-wavey to me.
I also need a precision voltage reference, at +10.000ish volts.
So here's my plan so far (attached).
Should I not gang the smartpin groups? Should I reduce the current/design limits for those to make it impossible to overdraw the main power budget?
Is there really a simpler way to do this, given that my main power rail is +12V and I need analog, digital, and precision sources at multiple levels?
[img][/img]
I use a switcher to 3.6V and then a dual LDO for PA and PB sides. The same switcher also produces 1.8V. I'm not saying do it exactly this way, but certainly reduce the input voltage to the 3.3V LDOs so that while it regulates out the ripple, it also does so efficiently and with low noise and good load transient response at the same time. The 1.8V should always be switched in my opinion as that is the only efficient way to do so and there is no need to worry about minor ripple on this supply.
I also note that "low noise" regulators seem to be more so because of the size and type of caps they recommend, so pay attention to this and the layout.
An alternative is to look at 12V SMPS parts like AP62300/AP62301 - those are Buck from VIN: 4.2V to 18V 75mΩ high-side power MOSFET and a 45mΩ Low side
The part codes give 2 choices, of burst or continuous.
Burst has lower idling power, but has more ripple.
You then go from 12V to 1.8V and 12V to something OK for linear 3v3 regulators - maybe ~ 4V ?
Or, if your 3v3 current needs expect to be low, you could look at a part like LDL212PV33R, which goes direct from 12V to 3v3, or the NCV8730BMTW330TBG, or the larger NCV8775CDT33RKG, could suit more industrial PCB designs.
I'm reworking the power net to be safer and more targeted for purpose. (fewer LDOs, less over-budget margin, lower LDO step down)
I was considering that I might need the +5V in some cases, but it is better to take an intentional approach to using 3.3V peripherals and then only add 5V from the 12V main if unavoidable. Also, I'd rather know that the current budget is not subject to peak demands from the core.
So, I'll probably just do 12Vmain->3.6V switched->1.8V switched + 3.3V LDO with only 2 LDOs for the VXXXX pins.
I'm presuming this is specifically for the 180Mhz clock speed. At 1.9V this ends up being about 1.2A.
Just some data points for consideration, if my math is accurate:
If the current draw scales linearly with core clock, that means it *might* be possible to hit 2.3A at 320Mhz @1.9V with the above test.
At a core voltage of 1.8, this goes down slightly to about 2.15A.
I presume it may be necessary to bump voltage slightly to maintain stability at higher clock rates.
- independent current supplies for 1.8v and 3.3v
- discrete switcher (AP62300 as suggested by jmg) The cost of the integrated module wasn't justifiable, and relied heavily on external filtering anyway.
- About 1/3 the original cost (even including the precision reference)
- LDO V headroom is now .3V (as suggested by Peter)
I've attached an updated infographic to illustrate the improvements. It seems so much easier now in retrospect than it did before. Thanks again!