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Hey Ken/Chip — Parallax Forums

Hey Ken/Chip

rjo__rjo__ Posts: 2,114
in Propeller 2
https://communities.intel.com/thread/126317

I can do this with P2s... In large number. I like Peter's board, and it will be possible to do demo's with it, but as a final design it would be a royal pain.

And of course I want 28nm.

I can easily imagine several ways to get it done. With your permission, I would like to open a discussion with Intel... not representing Parallax, but just trying to see if we could find a mutually acceptable direction.

Thanks,

Rich

Comments

  • Ken GraceyKen Gracey Posts: 7,390
    edited 2018-06-13 14:27
    Of course - talk with them. Thanks,

    Ken Gracey
  • cgraceycgracey Posts: 14,134
    Yes, we could really use their 14nm Tri-gate technology. 2GHz+ possible for our current design, and lots of on-chip RAM.
  • David BetzDavid Betz Posts: 14,516
    cgracey wrote: »
    Yes, we could really use their 14nm Tri-gate technology. 2GHz+ possible for our current design, and lots of on-chip RAM.
    But don't you have to redesign the instruction set for >1MB of hub RAM?

  • cgraceycgracey Posts: 14,134
    David Betz wrote: »
    cgracey wrote: »
    Yes, we could really use their 14nm Tri-gate technology. 2GHz+ possible for our current design, and lots of on-chip RAM.
    But don't you have to redesign the instruction set for >1MB of hub RAM?

    We would have to implement some paging scheme (per cog) in upper memory, or something.
  • rjo__rjo__ Posts: 2,114
    Will do.

    Thanks,

    Rich
  • Peter JakackiPeter Jakacki Posts: 10,193
    Will that make it a P2X16C4G64P-2G chip then? :)
  • David BetzDavid Betz Posts: 14,516
    cgracey wrote: »
    David Betz wrote: »
    cgracey wrote: »
    Yes, we could really use their 14nm Tri-gate technology. 2GHz+ possible for our current design, and lots of on-chip RAM.
    But don't you have to redesign the instruction set for >1MB of hub RAM?

    We would have to implement some paging scheme (per cog) in upper memory, or something.
    Ah, page tables, virtual memory, a translation look aside buffer. We can run Linux!
  • TorTor Posts: 2,010
    Ah, page tables, virtual memory, a translation look aside buffer. We can run Linux!
    .. or emulate an old minicomputer. I've already got Linux (everywhere) :)
  • Heater.Heater. Posts: 21,230
    David,
    We can run Linux!
    Noooo....

    Well, OK, put a RISC V core in there to run Linux. Let the COGs do what they are designed for.
  • ErNaErNa Posts: 1,752
    We do not want to do what others do! Innovation comes from leaving the path used. Like, denuking NK by buying their nukes and stop local production.
  • David BetzDavid Betz Posts: 14,516
    Heater. wrote: »
    David,
    We can run Linux!
    Noooo....

    Well, OK, put a RISC V core in there to run Linux. Let the COGs do what they are designed for.
    That sounds like a good plan to me.

  • Heater.Heater. Posts: 21,230
    ErNa,
    Innovation comes from leaving the path used.
    Yes. That is why I like to follow what goes on in the RISC V world. And the Propeller world of course. Putting the two together sounds just great.

    Let's hope that straying from the well trodden path does not result in falling off a cliff !



  • David BetzDavid Betz Posts: 14,516
    Heater. wrote: »
    ErNa,
    Innovation comes from leaving the path used.
    Yes. That is why I like to follow what goes on in the RISC V world. And the Propeller world of course. Putting the two together sounds just great.

    Let's hope that straying from the well trodden path does not result in falling off a cliff !


    Unfortunately, I think it often does. Not a reason not to do it though. Otherwise we’d never get anything new and different.

  • rjo__rjo__ Posts: 2,114
    edited 2018-06-15 17:27
    For my purposes, the instruction set is perfect. But I also recognize the huge desire of others to fully integrate with other OSs.

    You never know what you are missing if you let an opportunity go by.

    The RealSense people are having a hell of a time integrating their VPU in Windows 10 with C++... I don't think it is all their fault:) I don't know what high level language their VPU uses (if at all).

    For argument's sake... where would the P2 have to be on the nanometer scale to make sure the Prop can handle
    USB 3.1?

    That seems like a pretty good target.
  • AleAle Posts: 2,363
    Paging ? How about some really nice segment registers... I hear they come in 4 flavors. (ducks)
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