In keeping with your suggestion, perhaps P2 has eight "microcontroller cores" or the more terse term "cores" could be used after the first appearance of "microcontroller cores" in documentation.
That works for me
The Cortex M4's talk about a FPU, and Infineon mentions this on their Microcontrollers "16-bit Vector Computer (MDU+CORDIC) for Field Oriented Control"
Some care may be needed to separate Microcontroller from Microprocessor - ie P2 is a Microcontroller.
Is it? To me, and many other long-time embedded engineers, a microcontroller is a chip that will run totally stand-alone without any external chips, i.e. one that has its own internal non-volatile program memory.
Some care may be needed to separate Microcontroller from Microprocessor - ie P2 is a Microcontroller.
Is it? To me, and many other long-time embedded engineers, a microcontroller is a chip that will run totally stand-alone without any external chips, i.e. one that has its own internal non-volatile program memory.
Well, the continuum has blurred a little.
Microprocessor means Z80, x86, top end ARMs and things that can run Operating Systems.
Microcontrollers are deeply embedded parts, often run without operating systems.
It was common for oldest MCUs (8048, 8031) to use external memory, as the internal memory ones were very small. So 'internal code memory' was not mandated at all.
The P1 is certainly a Microcontroller (say so on the data sheet ) and it boots from serial memory, just like P2 does.
It's become very standard for processors with multiple processing units in them to call those cores. Intel/AMD CPUs, ARM CPUs (and MCUs using ARM sometimes will have multiple cores too), all the various GPUs use the term cores. I think it's become fairly known with the masses.
When I explain the Propeller to my friends I always use the term cores instead of cogs (with the aside mention that the docs and forums will often call them cogs).
I agree with you Ken, that it's a good idea to try and use industry standard terms for things as much as possible. It will make it easier to explain to people and sell to them.
I'm quite happy to not say "cogs", so I have updated the datasheet! I changed it to "corses", that's right, isn't it Ken?
From my pov I see each core more like a full 32-bit CPU albeit with a 20-bit address bus in that it can run code from anywhere in that memory space and it has 496 "registers" that are so flexible you can even run code from them!
When it comes to describing this chip for the likes of Mouser and Digikey we have a problem. It doesn't have any UARTS, yet it has 32 of them. It doesn't have any A/D, yet it has 64 channels, but when we say channels, we mean fully independent and simultaneous conversions. P2 doesn't have any PWMs, yet it has 64 of them etc etc. I know with FPGAs we can say "logic elements" etc and so we know that they can be turned into whatever we need, within reason. But the Smartpin is a bit like an FPGA per pin, it is so so configurable, and we have 64 of them so we could almost say "Realtime programmable I/O Array"
A microcontroller's ISA is normally geared for controlling I/O and bit-banging etc whereas a CPU might not have any special I/O instructions etc. An 8051 has bit instructions that set or clear or xor or test or jump etc. An ARM doesn't although they did introduce horrible bit-banding but once again each pin may have a limited number of alternate configurations but they not programmable in the sense that P2 is, not by a long shot.
After all this, coming back to this post I'm thinking that the Mouser and Digikey need to have a special column or two in their lists just for P2 since it is in a class of its own. It has 64 programmable peripherals distributed as one per pin and shared equally between all processor cores. Sure, we call them smartpins, but we have to think how to describe them for parts searches, for ads, and as general specifications. Then to there are the cores and do we say MIPS/core or total MIPS since I notice this is what XMOS does with its "logical" cores.
How on earth are we going to be able to describe this chip for parts searches?
In keeping with your suggestion, perhaps P2 has eight "microcontroller cores" or the more terse term "cores" could be used after the first appearance of "microcontroller cores" in documentation.
I don't think there is any need to call them "microcontroller cores". Just "cores" should be fine. The entire chip is a microcontroller.
In keeping with your suggestion, perhaps P2 has eight "microcontroller cores" or the more terse term "cores" could be used after the first appearance of "microcontroller cores" in documentation.
I don't think there is any need to call them "microcontroller cores". Just "cores" should be fine. The entire chip is a microcontroller.
True, but Ken's words of " P2 has eight "microcontroller cores" reinforces that those are actually eight fully independent copies of the same thing, not some single core and a fast MUX, giving 'virtual cores'
How on earth are we going to be able to describe this chip for parts searches?
List each peripheral type as 64 peripherals with a global note for total combined of 64 peripherals (64 I/O pins). Granted, it's not a completely clear way but it's not wrong either. The "Note:" should start the questions rolling. Which is the best thing, imho.
In keeping with your suggestion, perhaps P2 has eight "microcontroller cores" or the more terse term "cores" could be used after the first appearance of "microcontroller cores" in documentation.
I don't think there is any need to call them "microcontroller cores". Just "cores" should be fine. The entire chip is a microcontroller.
True, but Ken's words of " P2 has eight "microcontroller cores" reinforces that those are actually eight fully independent copies of the same thing, not some single core and a fast MUX, giving 'virtual cores'
I guess you're worried because XMOS incorrectly calls "virtual cores" just "cores"? I that case I don't see how adding "microcontroller" helps. Maybe they should be called "fully independent cores"?
And we did not yet started trying to find a good "name" to fully explain the roles that can be played by the eight STREAMERS.
They could simply not fit into some restricted class, like "eight units, 1-to-32-bit wide, high speed I/O bit-bangers", nor they are that limited to be fully described as being "mere" "eight 32-bit wide DMA channels".
Eight transputer channels? I dont think so (despite it could help many shinny and refratary heads, to gain a brand new layer of growing hair).
And we did not yet started trying to find a good "name" to fully explain the roles that can be played by the eight STREAMERS.
They could simply not fit into some restricted class, like "eight units, 1-to-32-bit wide, high speed I/O bit-bangers", nor they are that limited to be fully described as being "mere" "eight 32-bit wide DMA channels".
Eight transputer channels? I dont think so (despite it could help many shinny and refratary heads, to gain a brand new layer of growing hair).
I suppose if we can have "smart pins" we can also have "smart DMA"? Certainly, "DMA" is a term people will understand probably better than "streamer".
How on earth are we going to be able to describe this chip for parts searches?
List each peripheral type as 64 peripherals with a global note for total combined of 64 peripherals (64 I/O pins). Granted, it's not a completely clear way but it's not wrong either. The "Note:" should start the questions rolling. Which is the best thing, imho.
List as 64 Smart Programmable Peripherals (anything better than peripherals?) each of which can be one of.... UART, I2C, SPI, USB (with additional software), PWM, ADC, DAC, SIN/Square/Sawtooth wave, etc, etc.
So yes, 32 UARTs, 32 I2C, 16 independent SPI, 32 USB, 64 independent PWM channels, 64 independent ADC, ??? DAC, etc.
it's going to be necessary to list all the possible peripherals, with the limitation being the number of I/O pins available (64). However, almost all peripherals can be on any pins, unlike other micros that have highly restrictive limitations on what can go where.
Each core has a PRNG, CORDIC, 32x32 multiply, 64x32 divide ???, SQRT, etc, 3x32-bit timers, 512x32- bit registers, 512x32-bit LUT (look up tables), and fast code can execute from the registers and lut, 8x32-bit internal stack, additional 2/4? Stack pointers.
Oh, and thanks Ken. I am really pleased you are supporting the use of CORES. As you probably know, I have been a long time proponent to using cores to describe the P1.
And I think we should refer the the P2 as an 8-core 32-bit microcontroller / microprocessor (micros). (note the space between microcontroller / microprocessor so either will come up on search engines).
How on earth are we going to be able to describe this chip for parts searches?
List each peripheral type as 64 peripherals with a global note for total combined of 64 peripherals (64 I/O pins). Granted, it's not a completely clear way but it's not wrong either. The "Note:" should start the questions rolling. Which is the best thing, imho.
Yes, I had thought of that also and to do so is quite valid since it does have all that but I wonder how that asterisk would work in those online searches. From a Mouser search I have isolated these headings along with a note or question:
Series - Is this the P2 series?
Core - It's not ARM or MIPS or PIC.... or is the P2 core?.
Maximum Clock Frequency - 180MHz? or 180MHz x8 or 1440MHz total?
Program Memory Size
Data RAM Size
ADC Resolution
Interface Type - Yes we have USARTSx32**, PWMx64*, ADCx64*, DACx64*, USBx??, I2C???, VGAx??, LIN??, CAN?? etc etc
* - Any mix of maximum 64 peripheral types total
** - Note - 32 Full Duplex USARTs or any mix of transmitters and receivers with independent baud rates.
Some of these peripherals are partly software and partly a core or two but also need supporting software that would almost have to be drag'n'drop like PSoC Creator where it would insert the code etc to support this "peripheral". Oh boy, I can see where this is going so maybe we just better feature the Prop in every magazine project we can think of as the next best thing or hope that Blocky provides the means for educators to turn a generation of school kids into P2 addicts (in a good way). Sometimes you only need it to be really really good at just one thing, at least initially for it to catch on.
How on earth are we going to be able to describe this chip for parts searches?
List each peripheral type as 64 peripherals with a global note for total combined of 64 peripherals (64 I/O pins). Granted, it's not a completely clear way but it's not wrong either. The "Note:" should start the questions rolling. Which is the best thing, imho.
List as 64 Smart Programmable Peripherals (anything better than peripherals?) each of which can be one of.... UART, I2C, SPI, USB (with additional software), PWM, ADC, DAC, SIN/Square/Sawtooth wave, etc, etc.
So yes, 32 UARTs, 32 I2C, 16 independent SPI, 32 USB, 64 independent PWM channels, 64 independent ADC, ??? DAC, etc.
it's going to be necessary to list all the possible peripherals, with the limitation being the number of I/O pins available (64). However, almost all peripherals can be on any pins, unlike other micros that have highly restrictive limitations on what can go where.
Each core has a PRNG, CORDIC, 32x32 multiply, 64x32 divide ???, SQRT, etc, 3x32-bit timers, 512x32- bit registers, 512x32-bit LUT (look up tables), and fast code can execute from the registers and lut, 8x32-bit internal stack, additional 2/4? Stack pointers.
Oh, and thanks Ken. I am really pleased you are supporting the use of CORES. As you probably know, I have been a long time proponent to using cores to describe the P1.
And I think we should refer the the P2 as an 8-core 32-bit microcontroller / microprocessor (micros). (note the space between microcontroller / microprocessor so either will come up on search engines).
I would think that to be called a microprocessor it would have to be able to execute code from external memory. I think microcontroller is more appropriate.
I would think that to be called a microprocessor it would have to be able to execute code from external memory. I think microcontroller is more appropriate.
Exactly my thought. A microprocessor has an exposed address and data bus. An I2C port does not a microprocessor make.
In keeping with your suggestion, perhaps P2 has eight "microcontroller cores" or the more terse term "cores" could be used after the first appearance of "microcontroller cores" in documentation.
"microcontroller cores" followed by "cores" throughout the rest of the document seems the best approach to me. I can't imagine anyone in the Parallax community not understanding this terminology and certainly everyone outside the community will understand it. Yea... probably some will cry about walking away from "cogs" but I think it's the right thing to do.
In keeping with your suggestion, perhaps P2 has eight "microcontroller cores" or the more terse term "cores" could be used after the first appearance of "microcontroller cores" in documentation.
"microcontroller cores" followed by "cores" throughout the rest of the document seems the best approach to me. I can't imagine anyone in the Parallax community not understanding this terminology and certainly everyone outside the community will understand it. Yea... probably some will cry about walking away from "cogs" but I think it's the right thing to do.
What does "microcontroller cores" instead of just "cores" buy you? Of course these are microcontroller cores. The whole chip is a microcontroller. Adding "microcontroller" seems redundant and not particularly helpful.
"microcontroller cores" followed by "cores" throughout the rest of the document seems the best approach to me. I can't imagine anyone in the Parallax community not understanding this terminology and certainly everyone outside the community will understand it. Yea... probably some will cry about walking away from "cogs" but I think it's the right thing to do.
What does "microcontroller cores" instead of just "cores" buy you? Of course these are microcontroller cores. The whole chip is a microcontroller. Adding "microcontroller" seems redundant and not particularly helpful.
[/quote]
It's just an additional self-documenting feature.
Sorta like this: when you come to Parallax we introduce you as David Betz. Moments later, we're referring to you as David. It's similar to spelling out an acronym the first time it is used, and then referring to it by the letters.
I'm not sure of the correct English explanation of what we're trying to achieve, but Phil Pilgrim can probably describe it properly. If you refer to the initial use as a microcontroller core, then readers know what kind of core you're talking about. If you don't do this, then they may be thinking "cores - some sort of RAM feature, or I/O pin thingie, or hole in the chip where data travels around?".
I have hardly contributed to P2 so I feel a bit funny jumping in the conversation with a silly request. But here I am.
I have hardly contributed to P2 so I feel a bit funny jumping in the conversation with a silly request. But here I am.
Ken Gracey
Rubbish Ken! Most of us know otherwise. You have tried to keep the P2 on the rails, certainly kept it funded, and have input at various times thru it's development. Now is especially your time, given your marketing expertise. Remember, Engineers are not known for their marketing abilities
What you are doing is managing context down, clarity up.
To that end, it may be worth doing, up front, a quick pass at "cog" so that too is introduced.
Its hard, because Chip calls em cogs. Many of us do. And that will likely fade some, but not go away entirely.
"Core" can gain ground organically that way. And peolle have just enough context to get along, low friction style.
Ie:
"Sometimes casually referred to as cogs"
"Also known as the hub"
"During development, these were called cogs and ot the hub"
...you get the idea.
Similar phrasing has been done before, and its enough for people to get and then proceed with few worries.
May be worth doing. We have a lot of code out there using those terms, and it's not like that will all ve changed. And its also not like we should be telling people what to do or say either.
Tackling it this way would leave everyone reasonably able to understand without the pile of meta discussion normally associated with managing this kind of thing.
To me, the P1 cog lacking execute from hub, is enough different from what most would expect of a core to warrant a different term.
The P2 has that hubexec, and does resemble what people would exoect from a core a lot more. Enough to warrant using core, IMHO.
I may not bother, but I will also not care should something I produce see edits.
Honestly, I do not see those terms as a primary barrier.
Positioning the device is.
The P2 is more than most would expect from a microcontroller, and less than many would say of a system on chip, though software may well improve things, imho. Tackling that well seems like big return for the effort.
List as 64 Smart Programmable Peripherals (anything better than peripherals?) each of which can be one of.... UART, I2C, SPI, USB (with additional software), PWM, ADC, DAC, SIN/Square/Sawtooth wave, etc, etc.
So yes, 32 UARTs, 32 I2C, 16 independent SPI, 32 USB, 64 independent PWM channels, 64 independent ADC, ??? DAC, etc.
it's going to be necessary to list all the possible peripherals, with the limitation being the number of I/O pins available (64). However, almost all peripherals can be on any pins, unlike other micros that have highly restrictive limitations on what can go where.
I've used the idea of practical limit, as you cannot easily/sensibly have 64 PWMs and still boot the P2. I think Single Pin boot got lost, so the 'practical max' is 62 (was 63) ?
For UARTS is may be smarter to use UARTpins=62, and then say any mix of TX/RX within that 62 ?
It's also a good idea to include a test examples, that show practical operation limits. eg 1 TX + 61 RX uarts, can run to what Baud rate on one core ?
Claims of 32 USB need care, as currently I think it consumes 2 cores to run USB. Does that make a practical limit 3 or 4 USB ? (certainly nowhere near 32 )
This is all food for thought and not to be taken literally and question marks are prompts for thought. We know what the problem is with the P1 when it is listed by Mouser/Digikey etc so let's think about how the "peripherals" can be listed and described.
This is all food for thought and not to be taken literally and question marks are prompts for thought. We know what the problem is with the P1 when it is listed by Mouser/Digikey etc so let's think about how the "peripherals" can be listed and described.
Maybe if Parallax had had a standard set of supported peripherals the idea of "soft peripherals" would have gained more traction outside of the forum community. As it is, the P1 comes with "potential peripherals" not "soft peripherals". There is nothing there out of the box and nothing officially supported by Parallax that I am aware of. Should this be changed with P2?
Maybe if Parallax had had a standard set of supported peripherals the idea of "soft peripherals" would have gained more traction outside of the forum community.
I would like to challenge the idea that the P2 only has "soft" peripherals.
As for the Smart Pins, I would describe them as "64 Reconfigurable Peripherals" which each can be configured to do any one of (List of capabilities) at any one time. Also, that each has a connection to a pin.
The CPU cores could then be described as "CPU Cores that can act as Soft Peripherals" as well.
I would like to challenge the idea that the P2 only has "soft" peripherals.
As for the Smart Pins, I would describe them as "64 Reconfigurable Peripherals" which each can be configured to do any one of (List of capabilities) at any one time. Also, that each has a connection to a pin.
The CPU cores could then be described as "CPU Cores that can act as Soft Peripherals" as well.
I agree, Reconfigurable Peripherals is more FPGA sector, and better than "soft peripherals" - there are a lot of silicon gates, aka counters and shifters, in those Smart Pin Cells
You could also say the "Deterministic CPU Cores that can act as Soft Peripherals"
Using existing industry terms leads to lots of inaccurate assumptions.
Maybe we need a whole new base term like "microcontroller" and "FPGA" genres have.
Simple sentences and phrases actually describe things well. I've always used "smart pin" as it is descriptive, while I've avoided "smartpin" as it's gimmicky and reads like a trademark.
A new genre name could be useful and gimmicky, but after that, maybe simple descriptions would suffice.
Just some thoughts. We are fighting decades of convention which have narrowed the meaning of otherwise-apt terminology.
Comments
The Cortex M4's talk about a FPU, and Infineon mentions this on their Microcontrollers "16-bit Vector Computer (MDU+CORDIC) for Field Oriented Control"
Is it? To me, and many other long-time embedded engineers, a microcontroller is a chip that will run totally stand-alone without any external chips, i.e. one that has its own internal non-volatile program memory.
Well, the continuum has blurred a little.
Microprocessor means Z80, x86, top end ARMs and things that can run Operating Systems.
Microcontrollers are deeply embedded parts, often run without operating systems.
It was common for oldest MCUs (8048, 8031) to use external memory, as the internal memory ones were very small. So 'internal code memory' was not mandated at all.
The P1 is certainly a Microcontroller (say so on the data sheet ) and it boots from serial memory, just like P2 does.
When I explain the Propeller to my friends I always use the term cores instead of cogs (with the aside mention that the docs and forums will often call them cogs).
I agree with you Ken, that it's a good idea to try and use industry standard terms for things as much as possible. It will make it easier to explain to people and sell to them.
From my pov I see each core more like a full 32-bit CPU albeit with a 20-bit address bus in that it can run code from anywhere in that memory space and it has 496 "registers" that are so flexible you can even run code from them!
When it comes to describing this chip for the likes of Mouser and Digikey we have a problem. It doesn't have any UARTS, yet it has 32 of them. It doesn't have any A/D, yet it has 64 channels, but when we say channels, we mean fully independent and simultaneous conversions. P2 doesn't have any PWMs, yet it has 64 of them etc etc. I know with FPGAs we can say "logic elements" etc and so we know that they can be turned into whatever we need, within reason. But the Smartpin is a bit like an FPGA per pin, it is so so configurable, and we have 64 of them so we could almost say "Realtime programmable I/O Array"
A microcontroller's ISA is normally geared for controlling I/O and bit-banging etc whereas a CPU might not have any special I/O instructions etc. An 8051 has bit instructions that set or clear or xor or test or jump etc. An ARM doesn't although they did introduce horrible bit-banding but once again each pin may have a limited number of alternate configurations but they not programmable in the sense that P2 is, not by a long shot.
After all this, coming back to this post I'm thinking that the Mouser and Digikey need to have a special column or two in their lists just for P2 since it is in a class of its own. It has 64 programmable peripherals distributed as one per pin and shared equally between all processor cores. Sure, we call them smartpins, but we have to think how to describe them for parts searches, for ads, and as general specifications. Then to there are the cores and do we say MIPS/core or total MIPS since I notice this is what XMOS does with its "logical" cores.
How on earth are we going to be able to describe this chip for parts searches?
True, but Ken's words of " P2 has eight "microcontroller cores" reinforces that those are actually eight fully independent copies of the same thing, not some single core and a fast MUX, giving 'virtual cores'
List each peripheral type as 64 peripherals with a global note for total combined of 64 peripherals (64 I/O pins). Granted, it's not a completely clear way but it's not wrong either. The "Note:" should start the questions rolling. Which is the best thing, imho.
They could simply not fit into some restricted class, like "eight units, 1-to-32-bit wide, high speed I/O bit-bangers", nor they are that limited to be fully described as being "mere" "eight 32-bit wide DMA channels".
Eight transputer channels? I dont think so (despite it could help many shinny and refratary heads, to gain a brand new layer of growing hair).
So yes, 32 UARTs, 32 I2C, 16 independent SPI, 32 USB, 64 independent PWM channels, 64 independent ADC, ??? DAC, etc.
it's going to be necessary to list all the possible peripherals, with the limitation being the number of I/O pins available (64). However, almost all peripherals can be on any pins, unlike other micros that have highly restrictive limitations on what can go where.
Each core has a PRNG, CORDIC, 32x32 multiply, 64x32 divide ???, SQRT, etc, 3x32-bit timers, 512x32- bit registers, 512x32-bit LUT (look up tables), and fast code can execute from the registers and lut, 8x32-bit internal stack, additional 2/4? Stack pointers.
Oh, and thanks Ken. I am really pleased you are supporting the use of CORES. As you probably know, I have been a long time proponent to using cores to describe the P1.
And I think we should refer the the P2 as an 8-core 32-bit microcontroller / microprocessor (micros). (note the space between microcontroller / microprocessor so either will come up on search engines).
Yes, I had thought of that also and to do so is quite valid since it does have all that but I wonder how that asterisk would work in those online searches. From a Mouser search I have isolated these headings along with a note or question:
Series - Is this the P2 series?
Core - It's not ARM or MIPS or PIC.... or is the P2 core?.
Maximum Clock Frequency - 180MHz? or 180MHz x8 or 1440MHz total?
Program Memory Size
Data RAM Size
ADC Resolution
Interface Type - Yes we have USARTSx32**, PWMx64*, ADCx64*, DACx64*, USBx??, I2C???, VGAx??, LIN??, CAN?? etc etc
* - Any mix of maximum 64 peripheral types total
** - Note - 32 Full Duplex USARTs or any mix of transmitters and receivers with independent baud rates.
Some of these peripherals are partly software and partly a core or two but also need supporting software that would almost have to be drag'n'drop like PSoC Creator where it would insert the code etc to support this "peripheral". Oh boy, I can see where this is going so maybe we just better feature the Prop in every magazine project we can think of as the next best thing or hope that Blocky provides the means for educators to turn a generation of school kids into P2 addicts (in a good way). Sometimes you only need it to be really really good at just one thing, at least initially for it to catch on.
"microcontroller cores" followed by "cores" throughout the rest of the document seems the best approach to me. I can't imagine anyone in the Parallax community not understanding this terminology and certainly everyone outside the community will understand it. Yea... probably some will cry about walking away from "cogs" but I think it's the right thing to do.
[/quote]
It's just an additional self-documenting feature.
Sorta like this: when you come to Parallax we introduce you as David Betz. Moments later, we're referring to you as David. It's similar to spelling out an acronym the first time it is used, and then referring to it by the letters.
I'm not sure of the correct English explanation of what we're trying to achieve, but Phil Pilgrim can probably describe it properly. If you refer to the initial use as a microcontroller core, then readers know what kind of core you're talking about. If you don't do this, then they may be thinking "cores - some sort of RAM feature, or I/O pin thingie, or hole in the chip where data travels around?".
I have hardly contributed to P2 so I feel a bit funny jumping in the conversation with a silly request. But here I am.
Ken Gracey
Rubbish Ken! Most of us know otherwise. You have tried to keep the P2 on the rails, certainly kept it funded, and have input at various times thru it's development. Now is especially your time, given your marketing expertise. Remember, Engineers are not known for their marketing abilities
To that end, it may be worth doing, up front, a quick pass at "cog" so that too is introduced.
Its hard, because Chip calls em cogs. Many of us do. And that will likely fade some, but not go away entirely.
"Core" can gain ground organically that way. And peolle have just enough context to get along, low friction style.
Ie:
"Sometimes casually referred to as cogs"
"Also known as the hub"
"During development, these were called cogs and ot the hub"
...you get the idea.
Similar phrasing has been done before, and its enough for people to get and then proceed with few worries.
May be worth doing. We have a lot of code out there using those terms, and it's not like that will all ve changed. And its also not like we should be telling people what to do or say either.
Tackling it this way would leave everyone reasonably able to understand without the pile of meta discussion normally associated with managing this kind of thing.
To me, the P1 cog lacking execute from hub, is enough different from what most would expect of a core to warrant a different term.
The P2 has that hubexec, and does resemble what people would exoect from a core a lot more. Enough to warrant using core, IMHO.
I may not bother, but I will also not care should something I produce see edits.
Honestly, I do not see those terms as a primary barrier.
Positioning the device is.
The P2 is more than most would expect from a microcontroller, and less than many would say of a system on chip, though software may well improve things, imho. Tackling that well seems like big return for the effort.
For UARTS is may be smarter to use UARTpins=62, and then say any mix of TX/RX within that 62 ?
It's also a good idea to include a test examples, that show practical operation limits. eg 1 TX + 61 RX uarts, can run to what Baud rate on one core ?
Claims of 32 USB need care, as currently I think it consumes 2 cores to run USB. Does that make a practical limit 3 or 4 USB ? (certainly nowhere near 32 )
I would like to challenge the idea that the P2 only has "soft" peripherals.
As for the Smart Pins, I would describe them as "64 Reconfigurable Peripherals" which each can be configured to do any one of (List of capabilities) at any one time. Also, that each has a connection to a pin.
The CPU cores could then be described as "CPU Cores that can act as Soft Peripherals" as well.
My 2 cents
Jason
You could also say the "Deterministic CPU Cores that can act as Soft Peripherals"
Maybe we need a whole new base term like "microcontroller" and "FPGA" genres have.
Simple sentences and phrases actually describe things well. I've always used "smart pin" as it is descriptive, while I've avoided "smartpin" as it's gimmicky and reads like a trademark.
A new genre name could be useful and gimmicky, but after that, maybe simple descriptions would suffice.
Just some thoughts. We are fighting decades of convention which have narrowed the meaning of otherwise-apt terminology.