The Ascenium Rocket processor has no instruction set
KeithE
Posts: 957
It's Friday - I didn't feel like decoding their webpage.
http://ascenium.com/
"The Ascenium Rocket processor eliminates the performance bottleneck of the classic CPU's deep instruction pipeline that has stalled CPU performance improvements for generations. The Rocket processor has no instruction set. Instead Rocket constructs a succession of hardware circuits in real time that implement the functional intent of the source code. Rocket is a breakthrough non-Von Neumann architecture that will change the world of computing!"
When I searched on google this pdf came up on the llvm site (Heater might like it because it has an FFT) which appears to explain it better:
https://llvm.org/ProjectsWithLLVM/Ascenium.pdf
http://ascenium.com/
"The Ascenium Rocket processor eliminates the performance bottleneck of the classic CPU's deep instruction pipeline that has stalled CPU performance improvements for generations. The Rocket processor has no instruction set. Instead Rocket constructs a succession of hardware circuits in real time that implement the functional intent of the source code. Rocket is a breakthrough non-Von Neumann architecture that will change the world of computing!"
When I searched on google this pdf came up on the llvm site (Heater might like it because it has an FFT) which appears to explain it better:
https://llvm.org/ProjectsWithLLVM/Ascenium.pdf
Comments
http://web.eecs.umich.edu/~mmccorq/media/SCTI906.pdf
Looks like Ascenium did not get off the ground.
These kind of ideas seem to have been kicking around for ages. Instead of a big fat sequential processor lets have lots of little skinny processors working in parallel. Problem seems to be that nobody has managed to get a compiler for such a machine working properly.
The idea is not totally dead. People like Microsoft will rent you time on huge arrays of FPGA that you can configure to do what you like.
-Phil
-Phil