LVDS signalling

cgracey

I am going to run some simulations tonight and try to get a rough handle on LVDS, just out of curiosity. That 5Gb/s could be achieved in 180nm is compelling.

I wonder if, perhaps, in the interior, things are maintained as single-ended signals, but then become differential signals for I/O.

Beau Schwabe

One of the tricks is to use multi phase clocking to achieve the higher throughput speeds. The process itself can only handle about 300MHz for a single clock, but using "ring oscillator" tricks to phase shift or stagger multiple clock signals you can achieve a much higher throughput way above the process limitation you have with a single clock.

cgracey

I see. I've heard the only clock is typically the word clock. The bits just fly through inverters and the chain gets tapped at every Nth inverter to register the bits. Those systems are adaptive and don't really need a baud rate.

Does anyone know if a strict baud rate is typical in LVDS signaling?

Yanomani

Hi Chip

As usual, there is also another interesting publication from TI...

LVDS Owner’s Manual

ti.com/lit/ug/snla187/snla187.pdf

Simply a lot of everything about it...

Have you ever heard about it?

Beau Schwabe

The inverters form a delay line that suffices for a phase delay you would get from a ring oscillator ... the propagation delay within the inverters themselves can limit your overall frequency though. Think outside the box a little .... Think of timing latency you have with different wire lengths where you want the signals to arrive all at the same time... Now use that to your advantage in the opposite way of thinking where the goal is for the signals to arrive at a slightly different time in step to the original clock signal. This way you are not relying on the gate propagation delay. To complete the "ring oscillator" the main clock is controlled with a PLL by comparing timing between the "first and last" phase as well as the "first and second" phase to generate the proper PLL error tracking.

cgracey

Beau Schwabe wrote: »

The inverters form a delay line that suffices for a phase delay you would get from a ring oscillator ... the propagation delay within the inverters themselves can limit your overall frequency though. Think outside the box a little .... Think of timing latency you have with different wire lengths where you want the signals to arrive all at the same time... Now use that to your advantage in the opposite way of thinking where the goal is for the signals to arrive at a slightly different time in step to the original clock signal. This way you are not relying on the gate propagation delay. To complete the "ring oscillator" the main clock is controlled with a PLL by comparing timing between the "first and last" phase as well as the "first and second" phase to generate the proper PLL error tracking.

I think I understand what you are saying, but implementations are even simpler, with the parallel register snatching data right off the delay line taps. This means just a word clock. No time for bit clocks.

cgracey

Yanomani wrote: »

Hi Chip

As usual, there is also another interesting publication from TI...

LVDS Owner’s Manual

ti.com/lit/ug/snla187/snla187.pdf

Simply a lot of everything about it...

Have you ever heard about it?

That's a great document. To run at these crazy speeds, the circuit topology must be very, very simple.

Yanomani

cgracey wrote: »

That's a great document. To run at these crazy speeds, the circuit topology must be very, very simple.

Look at page 15.... Answers are there

jmg

cgracey wrote: »

I think I understand what you are saying, but implementations are even simpler, with the parallel register snatching data right off the delay line taps. This means just a word clock. No time for bit clocks.

Well yes, but the secret sauce will be in the timing of the phase of those delay elements.
That comes down to special analog support, where instead of a VCO, the PLL analog signal varies the local supply voltage, to vary the delays.
Could be an Up/Down DAC ?

Beau Schwabe

cgracey wrote: »

I think I understand what you are saying, but implementations are even simpler, with the parallel register snatching data right off the delay line taps. This means just a word clock. No time for bit clocks.

Yes, but using the gate propagation delay of the line taps can limit your speed in the end.

Here is a Chip I put together for National Semiconductor for Gig Ethernet .... It required a 25MHz crystal that was wound up internally by a factor of 10 to 250MHz .... Using the 4 twisted pairs (LVDS) on the Ethernet cable, the 250MHz achieved 1Gig speeds with a 4-stage ring oscillator as I described above. The process itself would only allow for 350MHz, so with 250MHz there was a good margin of overhead. In this case propagation delay of line taps would have been too slow.

https://www.artisantg.com/TestMeasurement/90233-1/National_Semiconductor_DP83865DVH_Gig_PHYTER_V_10_100_1000_Ethernet_Physical_Layer

Beau Schwabe

Yanomani,

Something interesting about that article you posted from TI ....

Page 7 Introduction:
"National Semiconductor’s LVDS Owner’s Manual, first published in spring 1997, has been the industry’s “go-to
design guide” over the last decade. The owner’s manual helped LVDS grow from the original IEEE 1596.3-1996
Standard for Low-Voltage Differential Signaling (LVDS) for Scalable Coherent Interface (SCI) into the workhorse
technology it is today."

... I was part of the high speed communications division at National Semiconductor before I started work at Parallax.
One of my mentor's wrote much of the content in that LVDS Owner’s Manual.

rjo__

I don't understand any of this. I understand the concept of ordered differentials... but what is being transmitted? the differential from the last data?

Thanks

cgracey

rjo__ wrote: »

I don't understand any of this. I understand the concept of ordered differentials... but what is being transmitted? the differential from the last data?

Thanks

The data is transmitted serially as a +/- signal pair. A differential detector (which is higher-voltage?) determines 0 or 1. The data move very fast.

cgracey

I did a SPICE simulation where I ran a 5Gb/s toggle (or a 2.5GHz clock) into a series of shared-drain inverters, which are fastest. I used the slow/hot/low-V corner to model worst-case. It turns out that a 200ps signal propagates through only FOUR inverters before the next edge. This has got to be near the limit of what is possible.

To make this delay line tunable, you could current-starve those inverters and MAYBE get by using three inverters per bit period, pushing the phase-shift to 120 degrees, each. Then, you could tap off every third inverter to capture the data, inverting every other flop output to compensate for the 3/odd stages per bit.

There's still the matter of propelling this signal OUT of a pin pair. The CERN 5Gb/s circuit claims to use capacitively-coupled pre-emphasis on its output. Then, you must be able to make the differential input into an internal single-ended signal. I tried using the differential inverter topology from our VCO to make a data delay line, but even hotted up, the signal peters out within the delay line. The data delay line needs about the simplest topology possible, and that probably dictates single-ended inverters - that is, if it's going to handle 5Gb/s.

Yanomani

Beau Schwabe wrote: »

Something interesting about that article you posted from TI ....

Hi Beau Schwabe

In fact, I was sure you would recognize it as an old friend of yours (the article).

Due to the way I've done my initial queries, the second edition was the first I'd found; the stylish "N", that unforgetable National Semiconductor logo, soon made me remember that, many times, you'd mentioned as having worked there.

Good to know that one of your mentors did such a great job. Certainly you had many good learning sessions with him.

Henrique