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Mapping individual pins to RISC-V Minion Cores (proposal for Shakti M-Class Libre SoC) — Parallax Forums

Mapping individual pins to RISC-V Minion Cores (proposal for Shakti M-Class Libre SoC)

CongaConga Posts: 51
in Propeller 2
Found this interesting case of convergence.
I don't think that it's direct competition for P2, even if it were implemented already (it isn't, AFAIK).

The Shakti M-Class Libre SoC design described at

http://libre-riscv.org/shakti/m_class/

adds some twists to the Minion Cores and
seems to get closer to the Propeller with the following proposal:

"Proposal / Concept to include "Minion Cores" on a 7-way pinmux"
The proposal here is to add four extra pin-mux selectors
(an extra bit to what is currently a 2-bit mux per pin), and
for each GPIO bank to map to one of four such ultra-small "Minion Cores".

For each pin, Pin-mux 4 would select the first Minion core, Pin-mux 5 would select the second and so on.

While I am aware of general discussions on Minion Cores,
I don't remember and I could not find discussions on this exact idea.

Comments

  • Heater.Heater. Posts: 21,230
    What an odd document. It does not say who it's by or where they are.

    A little sleuthing an we find it is the Indian Institute of Technology Madras.

    I wonder if the Shakti is a real project or some undergrad CS student work.

    India is very big on the RISC V. Will be interesting to see what comes out of it all.
  • CongaConga Posts: 51
    Heater. wrote: »
    What an odd document. It does not say who it's by or where they are.

    Some background:
    'libre-riscv.org' is latest branch, created a week ago,
    of Luke Kenneth Casson Leighton's major project EOMA68
    (crowd-funded eco-conscious hardware):

    https://www.crowdsupply.com/eoma68

    'libre-riscv.org' hosts a wiki, and right now it seems to be used more like a workspace (recording technical info, ideas and status), not an outreach site.
  • jmgjmg Posts: 15,173
    Conga wrote: »
    Found this interesting case of convergence.
    I don't think that it's direct competition for P2, even if it were implemented already (it isn't, AFAIK).

    Closer to the P2 in core-count, is this variant (55nm, 9 cores, 512kB RAM)

    https://en.wikichip.org/wiki/greenwaves/gap8

    https://greenwaves-technologies.com/en/developer-kits/

    Looks real to the point of Eval boards, and the fancy ZIF socket means they can drop in the newest silicon...

    February 28, 2018 : "GreenWaves taped out its GAP8 late last year, and it’s expecting to receive samples right about… now. Evaluation boards will follow working silicon.
    Eventually, the chip will be priced in the single digits, with large orders (100,000 units) priced at about $5."

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