Well, you've definitely got errors:
- The first line "Reset...": The pull-up on P59 locks in Serial boot only. It prevents any attempt to boot from Flash or SD.
- The second line "try FLASH...": Says it'll fall back to SD. But there isn't any combinations in which Flash falls back to SD, or SD falls back to Flash.
So here's my assessment of Cluso's table of what the code does compared to what the Google doc claims (and may have been the intent)
P59 P60 P61 Actions Same as Google Doc
None None None Serial, Stop Yes
None None Up Flash, Serial, Stop No, missing first Serial 100ms block
None Up None SD, Serial, Stop Yes
None Up Up Flash, SD, Serial, Stop Absent
Up None None Serial, Stop Yes
Up None Up Serial, Flash, Stop No, claims Flash ignored
Up Up None Serial, SD, Stop No, claims SD ignored
Up Up Up Serial, Flash, SD, Stop No, claims Flash and SD ignored
Down None None Stop No
Down None Up Flash, Stop Yes
Down Up None SD, Stop Yes
Down Up Up Flash, SD, Stop Absent
Well, you've definitely got errors:
- The first line "Reset...": The pull-up on P59 locks in Serial boot only. It prevents any attempt to boot from Flash or SD.
- The second line "try FLASH...": Says it'll fall back to SD. But there isn't any combinations in which Flash falls back to SD, or SD falls back to Flash.
ok, I think I see an error (need time to check)..
- The first line "Reset..." says: If a pull-up on P59 it will try Serial (ie it waits some time) and if not valid (ie else) it will move to the next line and try FLASH. STOP.
- The second line "try FLASH..." says: If a pull-up on P61 it will try FLASH and if not valid (ie else) it will move to the next line and try SD. The code will try SD at code $fc108-fc110.
- The third line "try SD" says: If a pull-up on P60 it will try SD and if not valid (ie else) it will move to the next line and try Serial. My SD code will return to try serial.
- The fourth line "try Serial" says: If a pull-down on P59 it will STOP (ie it will not boot from Serial) else it will try SERIAL (which may be again).
So here's my assessment of what the code does compared to what the Google doc claims (and may have been the intent)
P59 P60 P61 Actions Same as Google Doc
None None None Serial, Stop Yes
None None Up Flash, Serial, Stop No, missing first Serial 100ms block
None Up None SD, Serial, Stop Yes
None Up Up Flash, SD, Serial, Stop Absent
Up None None Serial, Stop Yes
Up None Up Serial, Flash, Stop No, claims Flash ignored
Up Up None Serial, SD, Stop No, claims SD ignored
Up Up Up Serial, Flash, SD, Stop No, claims Flash and SD ignored
Down None None Stop No
Down None Up Flash, Stop Yes
Down Up None SD, Stop Yes
Down Up Up Flash, SD, Stop Absent
Wow, that's massive. Even if it has a few errors that's still way more than either the others.
None None Up Flash, Serial, Stop No, missing first Serial 100ms block
I can assure you the 100 ms does exist. I worked with Eric to iron out getting loadp2 to make use of it.
The 100 ms only triggers if a valid SPI boot is detected - uses a checksum at end of first 1 kByte I think. If not valid, it'll drop straight to serial after reading that first 1 kByte of the SPI device.
Up None Up Serial, Flash, Stop No, claims Flash ignored
Reading the source code, I can't see that sequence coming true either. The P59 pull-up means the SPI device is never checked. The test for P59 is first and serial is jumped to immediately. So the spi_ok flag won't get set, therefore the serial timeout will stop the cog.
EDIT: Same goes for the other two extra cases of P59 pull-up
Up Up None Serial, SD, Stop No, claims SD ignored
Up Up Up Serial, Flash, SD, Stop No, claims Flash and SD ignored
P59 pull-up check is first and the serial code doesn't recheck any pull-up/down states, so will always simply stop after the 60 second timeout.
Up None Up Serial, Flash, Stop No, claims Flash ignored
Reading the source code, I can't see that sequence coming true either. The P59 pull-up means the SPI device is never checked. The test for P59 is first and serial is jumped to immediately. So the spi_ok flag won't get set, therefore the serial timeout will stop the cog.
EDIT: Same goes for the other two extra cases of P59 pull-up
Up Up None Serial, SD, Stop No, claims SD ignored
Up Up Up Serial, Flash, SD, Stop No, claims Flash and SD ignored
P59 pull-up check is first and the serial code doesn't recheck any pull-up/down states, so will always simply stop after the 60 second timeout.
EDIT2: Removed a duplicate line.
Yes, I hadn't read the source but was going by Cluso's analysis of the code. I've updated the language in my post to make that clearer.
Oh, I thought you'd previously done your own testing and that's what you'd found. I can't make sense of what Cluso has written.
I've found Chip's documentation to be pretty bullet proof in general. Many times I've thought I found something wrong only to find I hadn't tested the cases correctly or I've just not understood. The smartpins were a good example, the terminology is consistent and precise but it took a lot of experimenting for me to grok the importance.
@MSwann Welcome to the forums.
This thread is for discussion of Tricks and Traps.
Please start a new thread with the appropriate title and you'll get a lot more help there.
I was replying to JonnyMac's post.
Anyway, seems unfortunate that the waitms/waitus stuff didn't use the full 64bit counter, instead of just the lower 32bits.
Anyway, seems unfortunate that the waitms/waitus stuff didn't use the full 64bit counter, instead of just the lower 32bits.
My guess is those functions are using the event hardware in the cog. Not sure how allocation is managed. Anyway, the event hardware also only has a 32-bit compare register. It never got upgraded to match the system timer.
My guess is those functions are using the event hardware in the cog. Not sure how allocation is managed. Anyway, the event hardware also only has a 32-bit compare register. It never got upgraded to match the system timer.
Here's the code from the latest interpreter that handles waitms() and waitus()
waitus_ getct w 'get ct now to minimize error
rdlong y,#@clkfreq_hub 'get clock frequency
qmul y,x 'multiply clock frequency by us/ms
getqx x
getqy y
cmp pa,#bc_waitus wz 'us or ms time unit?
mov z,##1000
if_z mul z,z
setq y 'divide by time unit
qdiv x,z
getqx x
add x,w 'add ct
jmp #pwct 'do WAITCT
pwct getct w 'a b a: POLLCT(tick)
cmpm w,x wc 'a b b: WAITCT(tick)
if_c jmp #pwct '| b
_ret_ popa x '| b
_ret_ muxnc x,_FFFFFFFF 'a
On the other hand, it might just be a signed 32-bit operation in the routine. And not using any hardware beyond the GETCT instruction. Then it'll just be a case of extending the routine to 64-bit operation.
I think Chip said he was dead out of space for the interpreter; I wonder if that drove the decision to limit the timing to 32 bits.
With more code, it could be achieved. There are 15 identical instructions in the BYTEFILL/WORDFILL/LONGFILL routine that would sure be nice to condense, somehow. Then, we'd have some pennies left over for a 64-bit WAITMS/WAITUS.
The "Mask" location is a list of longs, but the original P1 code has a shell & "less than" sign before each number.
Mask long |<0,|<1,|<2,|<3,|<4,|<5,|<6,|<7
long |<8,|<9,|<10,|<11,|<12,|<13
long |<14,|<15,|<16,|<17,|<18,|<19
long |<20,|<21,|<22,|<23,|<24,|<25
long |<26,|<27,|<28,|<29,|<30,|<31
It will not compile on the P2 unless I remove the shell & less-than sign.
What does that syntax actually mean?
And what should I change to make it work similar on the P2?
My conversion is still not working.
The only other questionable conversion I made was to 4 XOR calls.
The P2 compiler expected an End-of-Line after the 1st variable (wz), so I took off the 2nd variable (nr).
There is no “nr” in the P2.
So in your example, temp will be updated. You have to fix any code using NR in P1 code when converting to P2.
This is where I am hitting a wall.
I am having trouble interpreting the assembly code past this point.
There is 6 XOR calls that have this problem, not 4.
I don't know where to go from here.
Update:
nr seems to be a flag that keeps temp from being overwritten on the P1.
There is no “nr” in the P2.
So in your example, temp will be updated. You have to fix any code using NR in P1 code when converting to P2.
This is where I am hitting a wall.
I am having trouble interpreting the assembly code past this point.
There is 6 XOR calls that have this problem, not 4.
I don't know where to go from here.
Update:
nr seems to be a flag that keeps temp from being overwritten on the P1.
Yes. So you need to create another temporary register and use 2 instructions to cater for the nr, unless you are certain the overwriting doesn’t matter
So
Instr dest,src nr
Becomes
Mov temp,dest
Instr temp,src
Comments
Basically they are the same. My table tries to show how the ROM code works in sequence down the page. The net results are the same.
- The first line "Reset...": The pull-up on P59 locks in Serial boot only. It prevents any attempt to boot from Flash or SD.
- The second line "try FLASH...": Says it'll fall back to SD. But there isn't any combinations in which Flash falls back to SD, or SD falls back to Flash.
Postedit: Fixed language above.
Postedit - except I read it wrong
- The first line "Reset..." says: If a pull-up on P59 it will try Serial (ie it waits some time) and if not valid (ie else) it will move to the next line and try FLASH. STOP.
- The second line "try FLASH..." says: If a pull-up on P61 it will try FLASH and if not valid (ie else) it will move to the next line and try SD. The code will try SD at code $fc108-fc110.
- The third line "try SD" says: If a pull-up on P60 it will try SD and if not valid (ie else) it will move to the next line and try Serial. My SD code will return to try serial.
- The fourth line "try Serial" says: If a pull-down on P59 it will STOP (ie it will not boot from Serial) else it will try SERIAL (which may be again).
I can assure you the 100 ms does exist. I worked with Eric to iron out getting loadp2 to make use of it.
EDIT: Same goes for the other two extra cases of P59 pull-up P59 pull-up check is first and the serial code doesn't recheck any pull-up/down states, so will always simply stop after the 60 second timeout.
EDIT2: Removed a duplicate line.
Yes, I hadn't read the source but was going by Cluso's analysis of the code. I've updated the language in my post to make that clearer.
Sorry, for adding to the confusion.
I've found Chip's documentation to be pretty bullet proof in general. Many times I've thought I found something wrong only to find I hadn't tested the cases correctly or I've just not understood. The smartpins were a good example, the terminology is consistent and precise but it took a lot of experimenting for me to grok the importance.
Instead of using the cordic solver, how would one use the MUL instruction to do a 32-bit multiply ?
So are you avoiding the CORDIC solver because you want signed 32 bit MUL, or in order to get the work done faster?
This thread is for discussion of Tricks and Traps.
Please start a new thread with the appropriate title and you'll get a lot more help there.
Post such questions here.
To answer the question, the hardware for system timer events fires on msbit rather than rollover. So range is 2^31.
Anyway, seems unfortunate that the waitms/waitus stuff didn't use the full 64bit counter, instead of just the lower 32bits.
When I've made the mistake of replying there in the past I've then asked admin to remove my posts.
With more code, it could be achieved. There are 15 identical instructions in the BYTEFILL/WORDFILL/LONGFILL routine that would sure be nice to condense, somehow. Then, we'd have some pennies left over for a 64-bit WAITMS/WAITUS.
Oh oh, I replied in that post. Please remove it.
The following code makes a reference call to a location called "Mask".
There are 32 of these calls (1 for each pin).
The "Mask" location is a list of longs, but the original P1 code has a shell & "less than" sign before each number.
It will not compile on the P2 unless I remove the shell & less-than sign.
What does that syntax actually mean?
And what should I change to make it work similar on the P2?
It's been replaced with DECOD:
The only other questionable conversion I made was to 4 XOR calls.
The P2 compiler expected an End-of-Line after the 1st variable (wz), so I took off the 2nd variable (nr).
Is this the correct way to handle that?
So in your example, temp will be updated. You have to fix any code using NR in P1 code when converting to P2.
This is where I am hitting a wall.
I am having trouble interpreting the assembly code past this point.
There is 6 XOR calls that have this problem, not 4.
I don't know where to go from here.
Update:
nr seems to be a flag that keeps temp from being overwritten on the P1.
So
Instr dest,src nr
Becomes
Mov temp,dest
Instr temp,src