P2 Shuttle (2017)
Cluso99
Posts: 18,069
in Propeller 2
Chip,
Obviously I don't know exactly what you are testing with the shuttle, other than it is to do with the ring frame and I/O.
OnSemi has synthesised the P2 remainder for you. I presume this has gone far enough to be fairly sure its ok.
Might it be possible to add the P2 synthesis into the ring frame for the shuttle?
Would there be much expense to add it in (might OnSemi add the synthesis for free/cheap) so that a better test might be done?
I know you need access to some parts of the ring frame. Could those special pins be connected via a mux and a "test" pin, so that they would otherwise be connected to the P2 logic? If not, then just scarifice those P2 pins for the testing?
As for the ROM, its quite easy to just "initialise" a small program into Cog 0 that just gives a really basic uart load and run into that cog. No smarts at all.
This would give a number of usable P2 test chips, rather than just ring frames.
Your thoughts ????
Obviously I don't know exactly what you are testing with the shuttle, other than it is to do with the ring frame and I/O.
OnSemi has synthesised the P2 remainder for you. I presume this has gone far enough to be fairly sure its ok.
Might it be possible to add the P2 synthesis into the ring frame for the shuttle?
Would there be much expense to add it in (might OnSemi add the synthesis for free/cheap) so that a better test might be done?
I know you need access to some parts of the ring frame. Could those special pins be connected via a mux and a "test" pin, so that they would otherwise be connected to the P2 logic? If not, then just scarifice those P2 pins for the testing?
As for the ROM, its quite easy to just "initialise" a small program into Cog 0 that just gives a really basic uart load and run into that cog. No smarts at all.
This would give a number of usable P2 test chips, rather than just ring frames.
Your thoughts ????
Comments
Chip just said the shuttle run didn't happen and he is just getting it ready now, with tweaks by Treehouse. That is my understanding anyway.
It's true that OnSemi has run the synthesis for our Verilog code to see that it compiles and meets timing, in order to formalize their quotation, but they haven't gone through the 10-week process of doing a full physical place-and-route with clock-tree and scan-test insertion . That comes later. So, all we have to fabricate in the shuttle run are the pad frame components, built into a test chip.
Depends on what it takes to get you excited, maybe?
Chip,
That April test chip is still just the I/O pad test with no logic right?
That's right. But the full design will be waiting in the wings, ready to go to fab.
The test chip is electrically equivalent to the pads in the final chip. There have just been a lot of metal routing improvements.