P2 Shuttle (2017)

Chip,

Obviously I don't know exactly what you are testing with the shuttle, other than it is to do with the ring frame and I/O.

OnSemi has synthesised the P2 remainder for you. I presume this has gone far enough to be fairly sure its ok.

Might it be possible to add the P2 synthesis into the ring frame for the shuttle?
Would there be much expense to add it in (might OnSemi add the synthesis for free/cheap) so that a better test might be done?

I know you need access to some parts of the ring frame. Could those special pins be connected via a mux and a "test" pin, so that they would otherwise be connected to the P2 logic? If not, then just scarifice those P2 pins for the testing?

As for the ROM, its quite easy to just "initialise" a small program into Cog 0 that just gives a really basic uart load and run into that cog. No smarts at all.

This would give a number of usable P2 test chips, rather than just ring frames.

Your thoughts ????
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Comments

  • 20 Comments sorted by Date Added Votes
  • Dave HeinDave Hein Posts: 5,370
    edited October 2017 Vote Up0Vote Down
    Chip wrote this on September 24.
    cgracey wrote: »
    The test chip is off on the shuttle now and should be back in 12 weeks. Hopefully, we'll have this synthesis and integration all done around then, too.
    So it seems like the test chip is in the pipeline now, and it's doubtful that Chip could do what you're requesting for the current shuttle run. The integration will probably happen after the test chip is back in December, so it may be possible that a fully integrated chip could go through another shuttle run early next year.

  • Dave,
    Chip just said the shuttle run didn't happen and he is just getting it ready now, with tweaks by Treehouse. That is my understanding anyway.
    My Prop boards: P8XBlade2, RamBlade, CpuBlade, TriBlade
    Prop OS (also see Sphinx, PropDos, PropCmd, Spinix)
    Website: www.clusos.com
    Prop Tools (Index) , Emulators (Index) , ZiCog (Z80)
  • cgraceycgracey Posts: 8,902
    edited October 2017 Vote Up0Vote Down
    We've been holding up the ONC18 shuttle run, in order to get the edits made to the layout. After I review the changes, Treehouse will send the layout database to OnSemi and they will start the shuttle process. This should happen by mid-week this coming week.

    It's true that OnSemi has run the synthesis for our Verilog code to see that it compiles and meets timing, in order to formalize their quotation, but they haven't gone through the 10-week process of doing a full physical place-and-route with clock-tree and scan-test insertion . That comes later. So, all we have to fabricate in the shuttle run are the pad frame components, built into a test chip.
  • What? When did that happen? We were told the test chip went into the shuttle run 5 weeks ago. So now we're looking at the middle of January for the test chip to come back. So I'm with Cluso on this one. At this point you might as well integrate all the logic, and then do a shuttle run. This way you'll have a fully functional test chip in 20 weeks.
  • cgraceycgracey Posts: 8,902
    edited October 2017 Vote Up0Vote Down
    The late discovery of the layout problems interrupted the shuttle flow. We've needed time to get things straightened out. This week, the shuttle will take off.
  • I'm kind of surprised it didn't leave without you. ;) Excuse the pun.
    “What car did you learn to drive stick shift on?” == “What was the make and model of your first car?” -> Password reset! -- https://krebsonsecurity.com/2018/04/dont-give-away-historic-details-about-yourself/
  • The case may be that there's just us and one other customer. The other customer was very late, anyway.
  • This shuttle is going to return around the time that the main chip would be taped out. It may be that we delay the main chip tape-out long enough to find out if the custom pads are okay. Not sure what to do there, yet.
  • Only one path there. Hold, until you are sure. It's a lot of money. Needs to be right.
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  • potatohead wrote: »
    Only one path there. Hold, until you are sure. It's a lot of money. Needs to be right.
    I agree. What is the point of the shuttle to validate the pads if you don't wait for the results before taping out the full chip?
  • Yup.

    Do not taunt Happy Fun Ball! @opengeekorg ---> Be Excellent To One Another SKYPE = acuity_doug
    Parallax colors simplified: http://forums.parallax.com/showthread.php?123709-Commented-Graphics_Demo.spin<br>
  • Is there any word on how the test chip is going? The last I heard it went into the shuttle run on November 15. It had been stated somewhere else that the shuttle run takes 12 weeks, so the test chip should be done around the middle of February. Is that still the plan?
  • cgraceycgracey Posts: 8,902
    edited January 15 Vote Up0Vote Down
    OnSemi will have the test chip back to us in April, they said last week. It will be one week before Prop2 should be wrapping up - just enough time to determine if we can proceed with tapeout, or our I/O pads need some modification first.
  • That sounds great! 2018 should be an exciting year for the P2.
  • Dave Hein wrote: »
    That sounds great! 2018 should be an exciting year for the P2.
    Don't you mean "2018 will be ANOTHER exciting year for the P2"? :-)

  • David Betz,
    Depends on what it takes to get you excited, maybe?

    Chip,
    That April test chip is still just the I/O pad test with no logic right?
  • Roy Eltham wrote: »
    David Betz,
    Depends on what it takes to get you excited, maybe?

    Chip,
    That April test chip is still just the I/O pad test with no logic right?

    That's right. But the full design will be waiting in the wings, ready to go to fab.
  • cgracey wrote: »
    Roy Eltham wrote: »
    David Betz,
    Depends on what it takes to get you excited, maybe?

    Chip,
    That April test chip is still just the I/O pad test with no logic right?

    That's right. But the full design will be waiting in the wings, ready to go to fab.
    Sounding promising!

  • Is the test chip still on track for coming back in April?
  • In our last status meeting with On Semi, it was said that the test chip is coming back this month (March).

    The test chip is electrically equivalent to the pads in the final chip. There have just been a lot of metal routing improvements.
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