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P1v on a Prop123-A9? — Parallax Forums

P1v on a Prop123-A9?

David BetzDavid Betz Posts: 14,516
in Propeller 1
Has anyone used the Prop123-A9 board for playing with P1v?

Comments

  • ozpropdevozpropdev Posts: 2,792
    Yep
    A while back I made a P123-A9 test image based on P1V
    See here


    The P123-A9 board is a great board for P1V with tons of IO and the big FPGA gives you 1MB hub.
  • Heater.Heater. Posts: 21,230
    See here: http://forums.parallax.com/discussion/comment/1421880/#Comment_1421880

    Where you originally posted the question.
  • jac_goudsmitjac_goudsmit Posts: 418
    ozpropdev, can you post the source code to your project, or at least your .qsf and top-level Verilog file? I would like to add it to my P1V repo.

    If your source code is in Github or in a Git repository that I can reach from the internet, that would be even better.

    ===Jac
  • David BetzDavid Betz Posts: 14,516
    Heater. wrote: »
    See here: http://forums.parallax.com/discussion/comment/1421880/#Comment_1421880

    Where you originally posted the question.

    Oops, sorry. I realized after I posted that that it was hijacking an unrelated thread so I created a new one. Thanks for the pointer!

  • jac_goudsmitjac_goudsmit Posts: 418
    edited 2017-10-29 08:01
    Sorry to revive an old thread but I'd like to report that earlier today I created an fpga-123 A9 target in my P1V repo at https://github.com/JacGoudsmit/P1V. I don't have an FPGA-123 (unfortunately) so I can't test it any further than building it, so let me know if it works.

    I also did a lot of other maintenance lately so all the targets are now based on this hierarchy:
    Top level module (different for each target)
    Reset module
    Clock module (different between Altera, Xilinx and future platforms
    "Dig" module by Chip
    "Hub" Hub logic
    "Hub_mem" Hub ROM/RAM
    "Cog" instantiated 8 times by default)
    "Cog_alu" Arithmetic/logic unit
    "Cog_ram" RAM
    "Cog_ctr" counters, instantiated twice
    "Cog_vid" video

    The documentation has also been reorganized a little, and I have some more reorganization in mind. For example I want to "break out" the hub memory to the top module because that's where most of the interesting customizations have happened and will happen. I'm thinking of things like:
    • Different hub RAM size
    • Using SRAM or DDR RAM chips as hub RAM
    • Scrambled vs. unscrambled ROMs
    • Removal of ROM areas (e.g. font ROM in the DE0-Nano)
    • Alternate boot loaders etc.

    Meanwhile, Andy Silverman has been doing a lot of work on adding some cool features to the Digilent Nexys4 target, and I'll be adding the DE2 (Cyclone 2) target "real soon now".

    ===Jac
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