Seriously? That's an awfully slim margin -- especially when you factor in dealer and distributor discounts.
-Phil
Well, we'll see. We need to get to a smaller process to get the price way down. Or, make smaller variants that would cost less. This is the BIG version.
Some vendors get lower 1-off prices, on a 'promotion basis' where the 1,10,100 prices are all similar.
ie not the 'usual price curve'.
I think Altera do that, for example.
That means a 1-5 off sale is not really making money, but is seen as 'seeding interest', the 100+ sale is $1000, and that's where margins become sensible.
I would have expected singles to be $15-20, only getting into the $10 range in volume. At least initially.
I recall seeing P1 chips for sale in singles for like $12 or $15 back in the day when it was newer.
I'm all for open discussion but financials might be taking it a bit far.
That said, I will point out, yet again, that Parallax has never been your typical volume producer. They aren't really competing with Microchip or Arm. I'm pretty certain that changes the economic numbers. I suspect it's difficult for them to justify a large markup for low volume educational sales. Lots of customers with limited budgets.
Which in-turn means no large discounts on higher volumes - unless that high volume customer can singly order enough to lower the per unit fab costs.
I'm all for open discussion but financials might be taking it a bit far.
That said, I will point out, yet again, that Parallax has never been your typical volume producer. They aren't really competing with Microchip or Arm. I'm pretty certain that changes the economic numbers. I suspect it's difficult for them to justify a large markup for low volume educational sales. Lots of customers with limited budgets.
Which in-turn means no large discounts on higher volumes - unless that high volume customer can singly order enough to lower the per unit fab costs.
I agree with you - it's really not an appropriate topic to "open source" with customers. Transparency can be taken a bit too far. I can imagine this $5 discussion getting trolled along for a while in the future. These costs are simply a materials cost; they don't reflect R&D, testing, managing, marketing (no matter how minimal it will be), documentation, software, etc.
I'm all for open discussion but financials might be taking it a bit far.
That said, I will point out, yet again, that Parallax has never been your typical volume producer. They aren't really competing with Microchip or Arm. I'm pretty certain that changes the economic numbers. I suspect it's difficult for them to justify a large markup for low volume educational sales. Lots of customers with limited budgets.
Which in-turn means no large discounts on higher volumes - unless that high volume customer can singly order enough to lower the per unit fab costs.
I agree with you - it's really not an appropriate topic to "open source" with customers. Transparency can be taken a bit too far. I can imagine this $5 discussion getting trolled along for a while in the future. These costs are simply a materials cost; they don't reflect R&D, testing, managing, marketing (no matter how minimal it will be), documentation, software, etc.
Ken Gracey
Well, I'd be interested to know if I was a customer, just because I like to know how things work. Everyone knows there needs to be markup, and in the west it must be significant. Now, why is bottled water that costs $0.000001 to source more expensive than gasoline?
And bottled water in lots of places costs the same as soft drink.
But reality must dictate well more than $10 for a P2. Maybe a small P2 could go for less, and a mid range P2 could get close to $10.
Chip,
How does the ring frame scale with a smaller (die) P2? Is it all soft now, or is it a hard block that has to be severely reworked?
I guess the line crossing is when the discussion turns from fab run prices to unit costs. From there it's a short hop to speculation on final product pricing.
My guess is that the total cost to Parallax for the P2 will be around $5M. Amortising that over 1M chips would be $5 per chip, meaning a total cost of $10 per P2 chip. Even if Parallax were to minimise their profit per P2, that would be a minimum average sales price of $15 each P2, meaning ~$20 qty 1 to allow for volume users of ~$15 qty 10K. Ouch
Remember, a module and or board will follow many sales. Modules, most? Boards? A lot. Those margin dollars, coupled with education and other things balance this equation a bit better than just the raw figures do. Just saying! It's not so grim as it may look, but don't let us doddle over that.
Do the fabs (AMS for P1, or OnSemi for P2) require minimum yearly purchases?
Do they ask for a minimum number of wafers (monthly, quarterly, annually, ...)?
Always - if not from the fab then directly from the sales person. Sales people always ask for projections, minimum order quantities, etc. They want successful customers.
I'm known as the buzz-killer when topics like this come up. Some of the discussion is so open that it'll create future pricing problems and customer negotiation issues for Parallax as we begin to understand true costs and need to quote customers who think our costs are $5. Also, I'm pretty sure that OnSemi wouldn't want the details they've quoted Parallax shared on these forums.
I didn't wanted to know exact details, just wanted to know if they request minimum yearly purchases as that will require you to think in advance, very carefully, which version to develop first. As there could be many options:
1) The big IC with 16 cogs,
2) A medium size 8 cogs that will probably kill P1 after launch.
3) a smaller 2-4 cogs variant, smaller than P1 but much faster and cheaper.
It's difficult to know which one will be a sales success, and which one will bring more margin/profits. I really want you to have high success on the first IC, because that way we will have the other variants earlier.
One last thing, please remind Chip how important code protection can be for sales (IMHO). He don't like it, and I think he maybe understimate how many sales code protection can bring to P2.
It's just like making two different pcbs on a panel. The disadvantage is that whatever mix you decide upon, you can almost guarantee the sales volume will be different. However, you can adjust pricing to try and influence the mix.
"Multi-Project Reticle Design and Wafer Dicing under Uncertain Demand"
There'd be an additional $185k for NRE and test development for each different die, even if you could share the reticle set, which I'm quite sure they won't let you do.
Chip - what's the difference between the $100k number that mentioned earlier, and the $185k number? I've been skeptical of these claims of $100k gets you your own custom chip.
>...at the really advanced nodes (28nm and below), not much customization is possible, since you kind of have to stick with proven IP.
The big companies certainly develop custom IP for each chip. e.g. integrated radios. It is not trivial so tons of simulations have to be run at various operating points. I forget how many "corners" are tested, but it's more than you would guess. Here's just one example - https://www.broadcom.com/products/wireless/gnss-gps-socs/bcm47755#overview
There'd be an additional $185k for NRE and test development for each different die, even if you could share the reticle set, which I'm quite sure they won't let you do.
Chip - what's the difference between the $100k number that mentioned earlier, and the $185k number? I've been skeptical of these claims of $100k gets you your own custom chip.
>...at the really advanced nodes (28nm and below), not much customization is possible, since you kind of have to stick with proven IP.
The big companies certainly develop custom IP for each chip. e.g. integrated radios. It is not trivial so tons of simulations have to be run at various operating points. I forget how many "corners" are tested, but it's more than you would guess. Here's just one example - https://www.broadcom.com/products/wireless/gnss-gps-socs/bcm47755#overview
$100k for synthesis and place & route. $85k for test development, including wafer probe card. $65k for reticles and prototypes.
It seems that customization is much easier at larger process nodes, mainly due to lower risk cost. When a reticle set is $10M, you are less inclined to take chances, and more prone to use proven IP.
Code protection is out. I guess you did not get the memo. If I understand correctly it's just not possible.
Please nobody mention it to Chip. I can't imagine the P2 penetrating any market where code protection is a requirement (IMOH).
Purely selfishly, I'd rather have the chip as ASAP rather than think about any changes.
Not completely. The basic setup works, just needs a yet undefined higher voltage to burn the fuses. Test chip might give clarity there.
In-circuit burning might be not so easy, but pre soldering, on a rig, the fuses will work as expected.
In-circuit will also work if you can provide a third voltage and prevent components on those pins to get burned.
As far as I know the fuses are still in, but not as nice as hoped for.
So people who really NEED code protection can use it with some effort.
And I think this is fine like that. For one offs or small runs code protection is moot anyways and for larger or more important projects pre soldering programming of the fuses should be feasible.
And some of them could be programmed at parallax while testing the chips, like a serial number or some calibration value for the frequency without external clock if the most common customers need that at all.
Heater, I don't know, it can be. Or maybe the one that didn't get the memo were you, as I thought that protection was going to be out because it was no possible to reach the engineer or department that knows all details about protection implementation.
A common issue that usually happens when a medium sized company want to talk with a Fortune 100 with around $4 billion year sales. If OnSemi do not want to reply, there are many other companies that are more willing to talk.
Just one example:
Comprehensive IP Portfolio (http://www.pgc.com.tw/ipportfolio_0.htm)
Digital IP : 8051, 6502, 16-bits MCU, ARM9, ARM11, Cortex, ARM, ANDES, WDC, UART, JPEG, H.264, 10/100/1000 MAC, USB2.0, USB3.0, USB3.1 Controller, DDR2, DDR3, DDR4
Mixed Signal IP : ADC, DAC, Codec, PLL, Crystal Oscillator, LDO, POR, Bandgap, Voltage Regulator
High Speed Interface PHY : USB2.0/3.0/3.1, DDR2/3/4, SATAI/II/III, PCIe, HDMI, XAUI, MIPI
Special IO IP : I2C, 1394a IO, LVDS, PECL, SSTL-2, SSTL-18, SSTL-15, USB2.0/3.0/3.1 HSTC, PCI-X, 32K Crystal Oscillator
Memory IP : SRAM, ROM, Flash, OTP, MTP, FUSE, EEPROM
Analog IP : LDO, Buck/Boost PWM converter, PFC(Mixed/HV/BCD)
There'd be an additional $185k for NRE and test development for each different die, even if you could share the reticle set, which I'm quite sure they won't let you do.
Never mind, makes no difference. When Chip stated recently that there will be no protection bits, even if the hardware is still in there some how, I sighed a sigh of relief, At last we can move on and get this chip built.
Now it occurs to me to wonder... If that fuse hardware is still in there, it sounds like something that is uncharacterized and un tested. An undocumented feature. So anyone serious about code protection could not use it.
Heater, As I understand it, reliable fuse programming requires a higher than normal voltage. This either can't be done "in-circuit" or would require prohibitively expensive switching circuitry to pull off "in-circuit". Once Chip gets test chips, fuse blowing can be tested and characterized as the need (potential customers) arises. If no one wants it initially, there are higher priority tasks
Comments
But P2 is going to be wildly successful, so no worries!
Well, we'll see. We need to get to a smaller process to get the price way down. Or, make smaller variants that would cost less. This is the BIG version.
Some vendors get lower 1-off prices, on a 'promotion basis' where the 1,10,100 prices are all similar.
ie not the 'usual price curve'.
I think Altera do that, for example.
That means a 1-5 off sale is not really making money, but is seen as 'seeding interest', the 100+ sale is $1000, and that's where margins become sensible.
I recall seeing P1 chips for sale in singles for like $12 or $15 back in the day when it was newer.
That said, I will point out, yet again, that Parallax has never been your typical volume producer. They aren't really competing with Microchip or Arm. I'm pretty certain that changes the economic numbers. I suspect it's difficult for them to justify a large markup for low volume educational sales. Lots of customers with limited budgets.
Which in-turn means no large discounts on higher volumes - unless that high volume customer can singly order enough to lower the per unit fab costs.
I agree with you - it's really not an appropriate topic to "open source" with customers. Transparency can be taken a bit too far. I can imagine this $5 discussion getting trolled along for a while in the future. These costs are simply a materials cost; they don't reflect R&D, testing, managing, marketing (no matter how minimal it will be), documentation, software, etc.
Ken Gracey
Well, I'd be interested to know if I was a customer, just because I like to know how things work. Everyone knows there needs to be markup, and in the west it must be significant. Now, why is bottled water that costs $0.000001 to source more expensive than gasoline?
But reality must dictate well more than $10 for a P2. Maybe a small P2 could go for less, and a mid range P2 could get close to $10.
Chip,
How does the ring frame scale with a smaller (die) P2? Is it all soft now, or is it a hard block that has to be severely reworked?
Remember, a module and or board will follow many sales. Modules, most? Boards? A lot. Those margin dollars, coupled with education and other things balance this equation a bit better than just the raw figures do. Just saying! It's not so grim as it may look, but don't let us doddle over that.
Needs to get done. Now.
Do they ask for a minimum number of wafers (monthly, quarterly, annually, ...)?
Always - if not from the fab then directly from the sales person. Sales people always ask for projections, minimum order quantities, etc. They want successful customers.
I'm known as the buzz-killer when topics like this come up. Some of the discussion is so open that it'll create future pricing problems and customer negotiation issues for Parallax as we begin to understand true costs and need to quote customers who think our costs are $5. Also, I'm pretty sure that OnSemi wouldn't want the details they've quoted Parallax shared on these forums.
Ken Gracey
I didn't wanted to know exact details, just wanted to know if they request minimum yearly purchases as that will require you to think in advance, very carefully, which version to develop first. As there could be many options:
1) The big IC with 16 cogs,
2) A medium size 8 cogs that will probably kill P1 after launch.
3) a smaller 2-4 cogs variant, smaller than P1 but much faster and cheaper.
It's difficult to know which one will be a sales success, and which one will bring more margin/profits. I really want you to have high success on the first IC, because that way we will have the other variants earlier.
One last thing, please remind Chip how important code protection can be for sales (IMHO). He don't like it, and I think he maybe understimate how many sales code protection can bring to P2.
"Multi-Project Reticle Design and Wafer Dicing under Uncertain Demand"
http://vlsicad.ucsd.edu/Publications/Conferences/210/c210.ps
Chip - what's the difference between the $100k number that mentioned earlier, and the $185k number? I've been skeptical of these claims of $100k gets you your own custom chip.
>...at the really advanced nodes (28nm and below), not much customization is possible, since you kind of have to stick with proven IP.
The big companies certainly develop custom IP for each chip. e.g. integrated radios. It is not trivial so tons of simulations have to be run at various operating points. I forget how many "corners" are tested, but it's more than you would guess. Here's just one example - https://www.broadcom.com/products/wireless/gnss-gps-socs/bcm47755#overview
Please nobody mention it to Chip. I can't imagine the P2 penetrating any market where code protection is a requirement (IMHO).
Purely selfishly, I'd rather have the chip as ASAP rather than think about any changes.
No harm. But I see no reason for it to endure.
$100k for synthesis and place & route. $85k for test development, including wafer probe card. $65k for reticles and prototypes.
It seems that customization is much easier at larger process nodes, mainly due to lower risk cost. When a reticle set is $10M, you are less inclined to take chances, and more prone to use proven IP.
Not completely. The basic setup works, just needs a yet undefined higher voltage to burn the fuses. Test chip might give clarity there.
In-circuit burning might be not so easy, but pre soldering, on a rig, the fuses will work as expected.
In-circuit will also work if you can provide a third voltage and prevent components on those pins to get burned.
As far as I know the fuses are still in, but not as nice as hoped for.
So people who really NEED code protection can use it with some effort.
And I think this is fine like that. For one offs or small runs code protection is moot anyways and for larger or more important projects pre soldering programming of the fuses should be feasible.
And some of them could be programmed at parallax while testing the chips, like a serial number or some calibration value for the frequency without external clock if the most common customers need that at all.
Enjoy!
Mike
I agree. The work got done, and we've got another test to figure out viability. If it's viable, great!
Truth is, we get the "has program protection" check box. Whether it's done or not is another discussion.
Heater, I don't know, it can be. Or maybe the one that didn't get the memo were you, as I thought that protection was going to be out because it was no possible to reach the engineer or department that knows all details about protection implementation.
A common issue that usually happens when a medium sized company want to talk with a Fortune 100 with around $4 billion year sales. If OnSemi do not want to reply, there are many other companies that are more willing to talk.
Just one example:
Shuttle : http://www.pgc.com.tw/mpw5.htm
ONLINE QUOTE --->>> http://www.pgc.com.tw/rqf.asp
The name is MLM or MLR:
http://anysilicon.com/understanding-maskset-type-mpw-mlm-mlr-single-maskset/
"MLM (Multi Layer Mask) or MLR (Multi Layer Reticle) services help reduce the tapeout NRE cost (full maskset cost)."
"What is the catch with MLM? The drawback is the wafer price. While the NRE price decreases — the wafer price increases."
CUSTOMER REQUEST (SOC/ASIC/MLM) >>> http://www.pgc.com.tw/rqf.asp
Never mind, makes no difference. When Chip stated recently that there will be no protection bits, even if the hardware is still in there some how, I sighed a sigh of relief, At last we can move on and get this chip built.
Now it occurs to me to wonder... If that fuse hardware is still in there, it sounds like something that is uncharacterized and un tested. An undocumented feature. So anyone serious about code protection could not use it.
I'd rather prefer parallax to make P2 a sales success, be wealthy, and make a lot of P2 variants in the future.
Might it open up a new, perhaps unanticipated, market?