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Cluso's P1V: HUB RAM 64KB & Beyond, etc — Parallax Forums

Cluso's P1V: HUB RAM 64KB & Beyond, etc

Cluso99Cluso99 Posts: 18,069
in Propeller 1
Today I installed Quartus V17.0 and then compiled my P1V base code.

Still some errors which have always been there and I don't know how to solve. I had previously fixed a number of errors/warnings.

I compiled P1V for the BeMicroCV (A2). I have some errors I need to fix as I have files for the DeNano, BeMicroCV and DE2-11x? There files vary the number of cogs, hub ram, etc. Once fixed, I intend to make a config file fo the BeMicro CV A9.

Also on my list is trying to speed up the hub access from 2 clocks to 1 clock. This will permit 1:8 cog to hub access or 1:16 with 16 cogs.

Comments

  • jmgjmg Posts: 15,173
    If your Quartus lets you target the new Cyclone 10, it could be nice to get some comparative Speed & LUT reports ?
  • Cluso99Cluso99 Posts: 18,069
    Just been looking at my old P1V code.

    Seems I already have 1clock hub working :)
  • Peter JakackiPeter Jakacki Posts: 10,193
    What is of primary interest to me though is what kind of low-cost easy-to-use FPGA I could fit a full P1V into with what us makers wanted in the first place many years ago, more I/O, more RAM.
  • Cluso99Cluso99 Posts: 18,069
    Peter Jakacki wrote: »
    What is of primary interest to me though is what kind of low-cost easy-to-use FPGA I could fit a full P1V into with what us makers wanted in the first place many years ago, more I/O, more RAM.
    YES! That what we REALLY WANTED :):):)

    64 I/O has been done on the P1V and 64KB HUB RAM (although we wanted more if possible and it's easy to do). There is a small amount of hub ram which should be write protected, rom if you like. IIRC it's about the top 2-4KB - the booter and Spin Interpreter (my faster Spin Interpreter fits and works here too).

    I also have 4KB cogs working too!

    As for FPGAs that will fit this style P1V, most of the cheaper ones don't have enough memory for the hub and cog ram. IIRC the DeNano uses a Cyclone IV and only supports 48KB HUB RAM.

    BTW speeding up the hub ram to 1:8 was a one line change ;)
    I am fairly certain I verified it was working when I last played with P1V (just over 2 years ago).

    During the week I'll take a look at the FPGAs that should suit. How much hub ram would you like Peter?
  • jmgjmg Posts: 15,173
    Peter Jakacki wrote: »
    What is of primary interest to me though is what kind of low-cost easy-to-use FPGA I could fit a full P1V into with what us makers wanted in the first place many years ago, more I/O, more RAM.

    The 'more RAM' bumps you into quite large FPGAs, tho there is one outlier which is the 128k Bytes in Lattice Ultra plus, with 39io in QFN48, tho that does not fit 8 COGs...

  • Peter JakackiPeter Jakacki Posts: 10,193
    64k RAM would be ok as I can manage now with 32k fully loaded, with fat32, Ethernet servers, floating point, VGA etc etc. More ram will let me add even more but maybe I don't need 8 cogs if I create minimal hardware support for uarts so that a single cog can handle multiple high speed ports.
  • jmgjmg Posts: 15,173
    Peter Jakacki wrote: »
    64k RAM would be ok as I can manage now with 32k fully loaded, with fat32, Ethernet servers, floating point, VGA etc etc. More ram will let me add even more but maybe I don't need 8 cogs if I create minimal hardware support for uarts so that a single cog can handle multiple high speed ports.

    Another approach would be to use the large IO many of the Bigger FPGAs have, to support something like XIP via

    Dual QuadSPI SRAM or HyperRAM
    { HyperRAM (64Mb) is $1.63/1k, slightly cheaper than much smaller (1Mb) QuadSPI SRAM ($1.84/1k)
    &
    Dual QuadSPI Flash (DTR) , or HyperFLASH

    The Cyclone10 thread has tables of FPGA / BRAM and prices.

    Perhaps even a single QuadSPI Flash (DTR) can give enough performance for Tachyon, with a max'd clock ?

    That leaves HUB memory for pure Data use.
  • Cluso99Cluso99 Posts: 18,069
    Removing the video cuts a reasonable amount of LUTs. I can build with any configuration of video
  • jmgjmg Posts: 15,173
    On the topic of Memory, I see ISSI show new Serial SRAM larger than the 1M Microchip and OnSemi top out at currently./

    ISSI Serial SRAM and Low Pin Count SRAM

    Shows up to 4Mbit SPI SRAM, but still only 20MHz.

    Another possible 'middle ground' is latched SRAM, (256k x 16, 6mm x 8mm BGA48) where ADR & DATA can share pins, - uses more pins than Serial Memory, but a lot less than Separate ADR.DB memory, so this could pair with moderate sized FPGA, and give random access faster and easier than Serial SRAM or HyperRAM.
    -10 parts look to support a 18ns tWC,tRC

    It's a shame they seem to have overlooked the obvious Increment-on-read option, for burst access, in the latched SRAM.
  • Cluso99Cluso99 Posts: 18,069
    edited 2017-07-21 10:57
    I am going to see what fits into an iCE40UP5K QFN48.
    There is 15KB plus 128KB of SRAM available.

    For starters.....

    64KB Hub Ram
    4 Cogs 2KB Ram
    32 I/O
    Plus 4 I/O SPI for external SPI Flash to boot load 64KB Hub Ram
    No video
  • Peter JakackiPeter Jakacki Posts: 10,193
    That device certainly looks very interesting and usable too. I have downloaded the development software and I will take a serious look at it. Thanks!
  • KeithEKeithE Posts: 957
    Cluso99 wrote: »
    I am going to see what fits into an iCE40UP5K QFN48.
    There is 15KB plus 128KB of SRAM available.
    One cool thing - based on the following tweet, it sounds like there may be Icestorm support for it sometime.


  • David BetzDavid Betz Posts: 14,516
    Cluso99 wrote: »
    I am going to see what fits into an iCE40UP5K QFN48.
    There is 15KB plus 128KB of SRAM available.

    For starters.....

    64KB Hub Ram
    4 Cogs 2KB Ram
    32 I/O
    Plus 4 I/O SPI for external SPI Flash to boot load 64KB Hub Ram
    No video
    What board are you using for your iCE40UP5K tests?

  • jmgjmg Posts: 15,173
    David Betz wrote: »
    What board are you using for your iCE40UP5K tests?
    I'd expect iCE40UP5K-B-EVN

    Right now those Eval Boards are in stock at Digikey & Mouser ~ $60, & there are prices on the QFN48, but no stock showing yet.

    The Evalboard uses FT2322H (common across Lattice EVNs), but I think the FT4222H is another (cheaper,smaller) HS-USB way to get SPI flash programmed.
    Cluso99 wrote: »
    I am going to see what fits into an iCE40UP5K QFN48.
    There is 15KB plus 128KB of SRAM available.

    For starters.....

    64KB Hub Ram
    4 Cogs 2KB Ram
    32 I/O
    Plus 4 I/O SPI for external SPI Flash to boot load 64KB Hub Ram
    No video
    Good numbers. Why not > 64kB HUB RAM ?
  • Cluso99Cluso99 Posts: 18,069
    jmg,

    64KB Hub Ram means no change to current P1 software, just that its all ram rather than 32KB of ram and 32KB of rom. Probably will need a small amount of protected RAM (as ROM) at the top.

    So, any current software should work fine, provided 4 cogs are sufficient. This should make for easy debugging.

    Might then do 2 sets of P1 with....

    64KB Hub Ram
    3 Cogs 2KB Ram
    32 I/O (each P1 has full access just like existing cogs)
    No video

    Plus another COG with 2KB Ram with access to both sets of Hub Ram, utilising a hub slot in each hub.

    Hub slots would then be 1:4.
  • jmgjmg Posts: 15,173
    Cluso99 wrote: »
    jmg,

    64KB Hub Ram means no change to current P1 software, just that its all ram rather than 32KB of ram and 32KB of rom. Probably will need a small amount of protected RAM (as ROM) at the top.
    I was wondering if something like a common lower 32k was possible, with private upper 32k areas ?
    It may also be possible to have pointers access > 64k, indirect only ?

  • Cluso99Cluso99 Posts: 18,069
    Need to get the basics running first
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