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Prop 2 Fuse conundrum - Vpp ?! - Page 3 — Parallax Forums

Prop 2 Fuse conundrum - Vpp ?!



  • evanhevanh Posts: 11,062
    I should point out there is already 16 symmetrical Streamers that can provide burst data in this very fashion. But obviously can quickly become pin count limited.

    Just requires a little management to suit a particular interface.
  • jmgjmg Posts: 14,686
    .. and another company offers NV memory... this one targets the higher voltage/automotive nodes, and so is on 0.18um

    "The enhanced NeoEE is fully compatible with standard logic and Bipolar-CMOS-DMOS (BCD) process without the need for additional masks and process steps. The IP has been silicon verified at 0.18um/5V process, and technology development is underway for other 5V platforms."

    They also show

    "NeoMTP is fully compatible with logic process, needing zero additional masks for 3.3V IO devices and 5V IO devices. Both types use a standard logic process without the need for any additional thermal budget. NeoMTP technology can deliver NVM block in system/in field programmability, maintaining high reliability, endurance and data retention over 10 years at 85° C 3.3V gate oxide) and over 10 years at 125° C (5V gate oxide) without any extra manufacturing costs"

    and this for Flash, which does need more masks...

    "NeoFlash can be embedded in CMOS logic processes with only 2–3 additional non-critical masks. While floating gate flash technology requires a complex and expensive double poly process (needing up to 11 additional mask layers), NeoFlash’s single poly architecture and stripped-down manufacturing give it powerful advantages in the embedded flash category, especially in advanced nodes"
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