Attaching verilog components to FPGA Propeller 1 design

escher

Hello all.

I've managed to load the Propeller 1 open-source FPGA design onto my DE0-Nano board.

I would like to be able to test my peripherals on the design BEFORE I order the physical parts.

For example, I need to be able to accept 16 different physical user inputs, and therefore I'm designing to feed them into daisy-chained parallel-to-serial shift registers. The Propeller will have PASM code running on a cog to accept the bits serially and parse them for the individual outputs.

The problem however is that I don't have enough experience with Quartus or Verilog to determine how to attach these peripheral signals to the Propeller design. The design has all the pins mapped to physical equivalents on the DE0 board by default.

Anyone with experience in this able to help me? Thank you!

Heater.

In Quartus you can change the pin assignments my selecting The "Assignments" menu then "Pin Planner". In the lower half of the resulting window is a spreadsheet like dialog that you can use to add/remove/change the signal to pin assignments.

You can also use "Assignments" -> "Assignment Editor" although I have never used that.

Heater.

I haven't looked at how the Propeller verilog is put together but I think that if you want to disconnect some I/O pins from the real FPGA pins you might want to create a new "top" module for yourself.

In your new top you will instantiate the Propeller and whatever new peripheral hardware modules you have. Your new top module would have all the same input output signals of the current Propeller top module. In you new top you would instantiate the Propeller and any new peripherals you have and "wire" them them up. Also wire them to the input/output signals.

You might get some inspiration on how to do this from looking at the top level module of my RISC V processor effort in Verilog for the DE0 Nano: https://github.com/ZiCog/xoro/blob/master/rtl/xoro_top.v

In there you can see how my top level module has input and outputs defined, how it instantiates the picrorv32 processor core and peripherals like memory and UART and how it wires them together.

Mind you, I'm only a Verilog beginner so this may not be the best way to proceed.

Heater.

I recommend exercising your new peripherals by themselves, wrapped in a test module (test bench), using the Icarus Verilog simulator. It's much easier faster to tweak code and test it under Icarus than waiting ages for Quartus to get stuff built for the FPGA.

When they look like they are logically correct it's time to drop them into Quartus.

escher

Hey @Heater. sorry I forgot to follow up. I ended up figuring it out pretty easily by just stepping through the top.tdf AHDL file. The outward facing pins on the DE0 such as the I/O pins are simply assigned to the propeller design outputs. All I had to do was basically declare my new module in the file, and assign the corresponding pins to where I wanted the Propeller to see them:

        include "ic_74HC165.inc"; -- 74HC165 shift register

... 

        sreg			: ic_74HC165; -- Instantiate my new module 

... 
        -- P8X32A pins

	core.pin_in[]	= prop_io[];

	pin[].in			= core.pin_out[];
	pin[].oe			= core.pin_dir[];

	prop_io[]		= (pin[31..14].out, sreg.Q7_n, sreg.Q7, pin[11..0]);  -- Replace a couple of the pins the Propeller exports with the outputs from my new module 

	-- 74HC165 pins

	sreg.CP		= prop_io[0];  -- Assign my new module's input pins to pins the Propeller exports so they can interact 
	sreg.CE_n	= prop_io[1];
	sreg.PL_n	= prop_io[2];
	sreg.DS		= prop_io[3];
	sreg.DN[]	= prop_io[11..4];

Heater.

That sounds like the ticket.

I had a brief look at the prop Verilog but gave up when I saw it had a AHDL top level. Why is that?

Surely a Verilog top level would make the design more usable. AHDL is Altera only as far as I can tell. It also precludes using the Prop Verilog from simulators such as Icarus or Verilator.

KeithE

I'm not sure which is the best repository to use. Might want to diff with https://github.com/jacgoudsmit/P1V if you're using the https://github.com/parallaxinc/Propeller_1_Design repository.

e.g. "2015-07-22 - (Jac Goudsmit) Fixed bug in PLL simulator ('&' in original source should be '|')"

It's been a while since I looked. I thought that someone had Xilinx targets, and that should address the top level AHDL. Edited to add: maybe that was in this now defunct repository https://github.com/jacgoudsmit/P8X32A_Emulation

escher

Heater. wrote: »

That sounds like the ticket.

I had a brief look at the prop Verilog but gave up when I saw it had a AHDL top level. Why is that?

Surely a Verilog top level would make the design more usable. AHDL is Altera only as far as I can tell. It also precludes using the Prop Verilog from simulators such as Icarus or Verilator.

Actually now that I've gone through the AHDL code I can tell you it's incredibly straightforward, and I believe it would be trivial to port it to a verilog format. The only complex element is the PLL instantiation:

pll				: altpll with (
						pll_type = "enhanced",
						operation_mode = "normal",
						inclk0_input_frequency = 20000,		-- 20000ps = 50MHz
						clk0_multiply_by = 16,
						clk0_divide_by = 5);

100% of the rest of the code is just simple pin and data assignments.

I'm pretty sure the reason for the AHDL is because the Digilent boards were just the best suited to hold the Propeller so they tailored the source to them. I'm not familiar at all with Icarus or Verilator though.

KeithE wrote: »

I'm not sure which is the best repository to use. Might want to diff with https://github.com/jacgoudsmit/P1V if you're using the https://github.com/parallaxinc/Propeller_1_Design repository.

e.g. "2015-07-22 - (Jac Goudsmit) Fixed bug in PLL simulator ('&' in original source should be '|')"

It's been a while since I looked. I thought that someone had Xilinx targets, and that should address the top level AHDL.

Thanks for the heads up. I'm pretty sure I pulled from the most up-to-date repo, but I'll make sure to double check.

Heater.

I have a very similar PLL instantiation in the top level Verilog of my little RISC V project. I'm sure that AHDL could be replaced with Verilog easily. That would be great for non-Altera FPGAs and the various simulators.

escher

Heater. wrote: »

I have a very similar PLL instantiation in the top level Verilog of my little RISC V project. I'm sure that AHDL could be replaced with Verilog easily. That would be great for non-Altera FPGAs and the various simulators.

One would also have to port the tim.tdf AHDL file, which generates all of the clock and counter signals, but I don't see any reason it would be difficult to either:

---------
-- TIM --
---------

subdesign tim
(
	clk						: input;
	res						: input;
	cfg			[6..0]		: input;

	clk_pll					: output;
	clk_cog					: output;
)

variable

	cfgx	[6..0]			: dff;
	divide	[12..0]			: dff;

begin

	cfgx[].clk				= clk;
	cfgx[].d				= cfg[];

	case cfgx[].q == b"11xx111" is
		when 1				=> clk_pll = clk;
		when 0				=> clk_pll = divide[11].q;
	end case;

	divide[].clk			= clk;
	divide[].d				= divide[].q + (
								 cfgx[].q == b"11xx111" # res,
								 cfgx[].q == b"11xx110" & !res,
								 cfgx[].q == b"11xx101" & !res,
								(cfgx[].q == b"11xx100" # cfgx[].q == b"xxxx000") & !res,
								(cfgx[].q == b"11xx011" # cfgx[].q == b"x1xx010") & !res,
								 b"0",
								 b"0",
								 b"0",
								 b"0",
								 b"0",
								 b"0",
								 b"0",
								 cfgx[].q == b"xxxx001" & !res
							  );

	clk_cog					= divide[12].q;

end;

"top" and "tim" are the only two AHDL files I see, however I don't know for sure if any of the other Propeller-specific files (e.g. not the Quartus project file, etc.) are only compatible with Quartus.

Here're my files if you're interested, maybe something will jump out at you.

escher

Scratch a lot of that, looks like someone was working on at least xilinx: https://github.com/jacgoudsmit/P1V/tree/xilinx/HDL

jac_goudsmit

Hi Escher!

Yes you should really use my P1V repository at https://github.com/jacgoudsmit/P1V. It has bug fixes that Chip Gracey himself posted in the forums, all the AHDL files were converted to Sysverilog, and I made some other improvements such as making it unnecessary to maintain 3 or more copies of the same code. All of this was originally based on Parallax's P1V repository and I filed pull-requests in the past to integrate my changes but got no response, so the Parallax P1V repo still has the bugs.

Before Parallax set up their own Github account, @MindRobots and others put the P1V sources into Github. I forked that repository and we did quite a bit of work in there, including extra features such as implementation of port B. The latest version of that still exists at https://github.com/jacgoudsmit/P8X32A_Emulation. It also had several supported Xilinx targets but they weren't integrated into the main tree yet (they were in separate subdirectories; you'll find them). The repo has been sort of abandoned until I have some time and motivation to integrate some changes into the P1V repo. I recently learned that it's possible to merge repos together, I might give that a try in the future but I'm very busy at work and on other projects.

So for now, the only Xilinx target that's supported in the P1V repo is the Arty board by Digilent (with a Xilinx FPGA). Unfortunately, the entire Propeller doesn't fit into the FPGA on the Arty so I had to reduce the number of cogs. It's not really clear to me why it didn't fit; I suspect that the problem can be solved by tweaking the settings of the Xilinx software.

===Jac

escher

Great thanks for the information! I honestly can't remember what repo I used for my P1V, but I haven't run into any problems yet.