The hub ram now loads from a file, significantly reducing the startup time. I also pre-load the booter into cog ram. That was easier than inserting the modified booter back into the rom image. The application shouldn't be able to tell the difference.
It took 4m16.791s to simulate 1 second. That's 1/256 real time. I used Retronitus as a stress test. I've simulated 9 seconds so far, sounds great!
I'm probably going to go back to P1V on iCE40 now. But, now I'll know that my verilog is good! :cool:
I'm amazed that one can "patch" chips with today´s feature sizes. And, as you say, the complexity of having to reverse engineer whatever the synthesis tools created for you. Sounds like something you really want to avoid having to do.
A mere $100,000 in the press release. Some guys I worked with used it in the last few years, and sometimes it worked. Sometimes not so well. When you're spinning a chip you want to leave as much intact as possible with the goal being to just change some metal layers and not cause any other issues with test logic etcetera.
I'm probably going to go back to P1V on iCE40 now. But, now I'll know that my verilog is good! :cool:
Are you using the IceStorm tools? Perhaps with an ICE40HX8K? Or are you using a larger part not supported by them? If it's IceStorm then I guess your biggest issue is some of the SystemVerilog code that Chip used for some muxing? And the PLL stuff mentioned in the USB thread?
Are you using the IceStorm tools? Perhaps with an ICE40HX8K? Or are you using a larger part not supported by them? If it's IceStorm then I guess your biggest issue is some of the SystemVerilog code that Chip used for some muxing? And the PLL stuff mentioned in the USB thread?
When I started this project IceStorm did not support PLLs. I'm just using the 12MHz oscillator directly. I'll worry about that later after the rest of it works.
Are you using the IceStorm tools? Perhaps with an ICE40HX8K? Or are you using a larger part not supported by them? If it's IceStorm then I guess your biggest issue is some of the SystemVerilog code that Chip used for some muxing? And the PLL stuff mentioned in the USB thread?
When I started this project IceStorm did not support PLLs. I'm just using the 12MHz oscillator directly. I'll worry about that later after the rest of it works.
I definitely agree that the PLL could come last. Are you able to simulate your design and it works there?
Which board are you using? The iCE40HX8K Breakout Board? Or something you built? I've been thinking about getting a breakout board. Some of the alternatives are nice but more costly and difficult to source.
Which board are you using? The iCE40HX8K Breakout Board?
That's the one! I have an iCEstick as well.
I started the verilator stuff to test the code. It's worked ok there. On the board, there is a lot of general weirdness happening. Things like jmp not working when jmpret does, and it depends on previous instructions or the location on memory. My last test case looped 4 times then stopped. I'm going to test with verilator first and if anything funny happens with IceStorm I'll try using iCEcube. It might be possible to build with iCEcube and load the ram contents with icebram.
All of these Verilog threads inspired me to buy a Lattice board. I'm sick of Quartus and the huge VM that I need to run it. Good luck with your efforts.
Also I was wondering if you've tried Icarus or some other simulator? There are some other free simulators (e.g. cver) and you can get a free version of Modelsim with an Altera/Xilinx install.
Also regarding simulation, can you run a gate level simulation via icebox_vlog? That might help.
Based on my past experiences, I'm always suspicious about the generated RAMs. Maybe you would write a simple memory test that would indicate status on some output pins?
Comments
It took 4m16.791s to simulate 1 second. That's 1/256 real time. I used Retronitus as a stress test. I've simulated 9 seconds so far, sounds great!
I'm probably going to go back to P1V on iCE40 now. But, now I'll know that my verilog is good! :cool:
I've seen a lot of hand patching during spins, but there was a tool released at one point to try to help. Synopsis ECO compiler - http://www.eetimes.com/document.asp?doc_id=1210223
A mere $100,000 in the press release. Some guys I worked with used it in the last few years, and sometimes it worked. Sometimes not so well. When you're spinning a chip you want to leave as much intact as possible with the goal being to just change some metal layers and not cause any other issues with test logic etcetera.
Are you using the IceStorm tools? Perhaps with an ICE40HX8K? Or are you using a larger part not supported by them? If it's IceStorm then I guess your biggest issue is some of the SystemVerilog code that Chip used for some muxing? And the PLL stuff mentioned in the USB thread?
When I started this project IceStorm did not support PLLs. I'm just using the 12MHz oscillator directly. I'll worry about that later after the rest of it works.
I definitely agree that the PLL could come last. Are you able to simulate your design and it works there?
Which board are you using? The iCE40HX8K Breakout Board? Or something you built? I've been thinking about getting a breakout board. Some of the alternatives are nice but more costly and difficult to source.
I started the verilator stuff to test the code. It's worked ok there. On the board, there is a lot of general weirdness happening. Things like jmp not working when jmpret does, and it depends on previous instructions or the location on memory. My last test case looped 4 times then stopped.
Also I was wondering if you've tried Icarus or some other simulator? There are some other free simulators (e.g. cver) and you can get a free version of Modelsim with an Altera/Xilinx install.
I'm also itching to get hold of an 8K Lattice board and trying IceStorm.
This is more like how simple HDL development should go:
Somebody should wrap that up with an IDE that is as simple as the Propeller tool or the Arduino IDE.
Based on my past experiences, I'm always suspicious about the generated RAMs. Maybe you would write a simple memory test that would indicate status on some output pins?
I used Quartus in the past. Have not tried any other simulators. I figured I would go with Verilator because it's fast.
http://zipcpu.com/zipcpu/2017/07/26/cpu-sim-debugger.html
Edit: maybe Heater will be inspired to build this type of project for RISC V ;-)