Did you made any changes at the pad frame layout, specially into the fuses area, and perhaps also had a chance to think about the possibility of having an I/O capability at the Reset signal?
To clear up the bewilderment around the apparent pace and focus of development on Parallax' part...
We are waiting to see how we are going to pay for the next steps, which are going to cost maybe $250k. We are being conservative in our approach here. While these expenses occur, Parallax needs to maintain positive cash flow. Until certain doors close/open, we are not sure about how we are going to address this matter. So, for now, I am working on the Spin interpreter, making little changes to the Verilog, along the way. I really can't imagine that there will be any more disruptive changes to the design between now and when we synthesize the final version. Meanwhile, all the analog layout changes have been made in the pad frame, based on the shortcomings of the last test chip. OnSemi will have a shuttle in July/August that we will run our new analog test chip on. That will probably come back in October. If everything is "go", we can proceed to make the final commitments to getting the silicon into production around or before that time frame.
Chip,
Do you mean another test chip like the previous one? ie not a usable chip, just a test of the outer ring??? If so, it seems a waste not to be able to test the rest of the chip, even if part has to have test pins instead of io pins.
Well, it would cost maybe over $100k to do the synthesis required for the full chip test. It would be good to know that the analog is okay before spending that much.
Sooner or later you will need to spend those $100k for the logic synthesis.
So I think that what Cluso means (and me too) is that it will be a complete waste if you do a shuttle test only for the complete analog outer ring without the inner logic, as you already paid all the 'real state' (7x7 mm, 49mm square).
Latest europractice MPW pricelist says around US $1,400 for each mm square. For 49 mm2, that will mean $68K for a 7*7mm shuttle.
But if the shuttle test is only for a small reduced outer part (left side, or right or top, or bottom side ... or even smaller) then the price of the shuttle can be reduced to $14K (as 10 mm2 is the minimum allowed MPW) and that would make sense.
But not sure, in that reduced shuttle test, if it will server the purpose of completely prove the outer ring.
But if the shuttle test is only for a small reduced outer part (left side, or right or top, or bottom side ...
Some months ago I already though about this idea: Just a side analog die with smartpins and I/O that could be packaged in a narrow DIP-16/18, SOIC-24/28, TSSOP-24/28 with just only between 10/20 pins per side at most.
Four of them can be put on all the sides of a FPGA (top, bottom, left, right). And all together (FPGA + 4x IO ICs sides) over a PCB can simulate a hybrid Propeller.
Then no need to make the inner synthesis.
Think that you will never be able to beat the logic density that current two-digits-nm FPGAs have. When the P2 came to live in the next 3 or 5 years, we probably will have the first single digit nm FPGAs, and the first ARM Cortex MCUs in 22nm FD-SOI process (from ST).
But if the shuttle test is only for a small reduced outer part (left side, or right or top, or bottom side ...
Some months ago I already though about this idea: Just a side analog die with smartpins and I/O that could be packaged in a narrow DIP-16/18, SOIC-24/28, TSSOP-24/28 with just only between 10/20 pins per side at most.
Four of them can be put on all the sides of a FPGA (top, bottom, left, right). And all together (FPGA + 4x IO ICs sides) over a PCB can simulate a hybrid Propeller.
Then no need to make the inner synthesis.
Think that you will never be able to beat the logic density that current two-digits-nm FPGAs have. When the P2 came to live in the next 3 or 5 years, we probably will have the first single digit nm FPGAs, and the first ARM Cortex MCUs in 22nm FD-SOI process (from ST).
The trouble is that there are maybe 20 internal connections from the core to each pin.
I have been following the P2 trail off and on for quite some time. I loved the P1 chip. But at this time I need a new list of what the P2 is going to be. The forums are encyclopedic and it's difficult to know what the P2 is right now. Maybe I missed a current list in the off times but, I'll know what I'll use it for when I get a clear picture of where things are at. Please advise.
The FPGA thread contains the latest information. The two links under "Documentation" list the instruction set, and describe the operation of the P2. The zip file contains the FPGA images, some sample programs and a text file that lists the instructions.
Chip,
Sorry, the following is a bit out of order, but I am on my iPhone and editing is a bit of a nightmare.
I had thought the outer ring (frame) had worked, and that subsequent changes were minor and without risk. This seems not to be the case???
If you have the time, why is another shuttle run required for testing the frame?
To minimise additional synthesis costs, mIght it be worth putting a P2 2-COG 64KB HUB into the space, with reduced I/O for your special pins?
If it works, then you have some spare chips to send a few to selected testers.
I know I really don't understand the process, but I had thought the frame had been sufficiently verified. Could you mix the testing pins out on port pins, with the mix defaulting to test on power up, and a special P2 instruction to flip them to I/O later. Would even provide software access to test the pins after being proven with your test bed.
It's also one of the reasons I suggested putting an expanded P1 into the frame. As long as some of the frame parts work (digital at least), then you would have a saleable P1 upgrade.
I guess my background just tells me to try and maximise the payback for expenditure, even if it means a little more expenditure.
Are you going to ask about internal FLASH, even it was only for your boot ROM?
It's also one of the reasons I suggested putting an expanded P1 into the frame. As long as some of the frame parts work (digital at least), then you would have a saleable P1 upgrade.
I don't think that is practical, as it represents both a distraction and lost time.
To minimise additional synthesis costs, mIght it be worth putting a P2 2-COG 64KB HUB into the space, with reduced I/O for your special pins?
If it works, then you have some spare chips to send a few to selected testers....
There may be some merit in this - if chip design P&R is anything like FPGA & PCB P&R, there is significant time spent in packing a final design, and I have often seen PCBs done on a faster/looser Autoroute setting, in order 'to get something the software guys can start with'.
In this case, you would drop the P2 COGS until P&R was ensured to be very quick.
This less-packed iteration, also gives valuable information on just what can fit along with 16 COGs.
Right now, that 512K memory, is a rather loose, aspirational target, but there may be some hard COGS or MEMORY decisions to make downstream.
Silicon usage would be poorer than a final design, but it does allow more to be tested, including the critical interfaces between Logic and the Custom ring.
Other benefits are final test coverage is better, and testing time is reduced.
I think this would also give a full PLL operation ?
Before we spend a lot of money to push Prop2 to completion, could you please help us identify likely markets for it and explain your rationale? Just a few sentences, or even one, would be appreciated.
Sounds like that's a conversation you should have had on day one.
The Prop2 is a real time processor in the truest sense of the word. Target real time markets. Machine equipment control isn't real time since the end product is predefined. Great market, but not real time. Process control is real time including the monitoring of tool wear, rocket control and the control of driverless cars. Maybe you should be talking to Elon Musk.
Prop2 will not be an educational 'tool' so NO BLOCKLY!
I'm not sure why "no blockly." Doesn't Blockly just translate blocks into a high level language (Spin or C statements for the propeller 1)? The only thing I see that is board dependent is for components on the board and predefined pins (e.g. ADC pins on the Activity Board). If C is available for the P2 wouldn't blockly support be a non issue?
Yeah Tom, you are right. Blockly support is going to be essentially free for P2, since it just targets C or Spin. It would just be a minor tweak to get it handling any P2 diffs.
Sandy,
P2 will be an educational tool, since Parallax is very big on education and everything they make is used for it. Heck even the ELEV8 stuff is... don't see why you would think otherwise.
I'm not sure why "no blockly." Doesn't Blockly just translate blocks into a high level language (Spin or C statements for the propeller 1)? The only thing I see that is board dependent is for components on the board and predefined pins (e.g. ADC pins on the Activity Board). If C is available for the P2 wouldn't blockly support be a non issue?
Tom
I think he means from a marketing perspective - the last thing you want tthe real-time commercial side who are most certainly the target audience to think this is a hobby processor for kids like the PickAx is.
Nothing more.
Personally I'm not sold on any Blockley implementation for any micro as a teaching tool. But then again schools seem to want it, so what can you do if you're a vendor except go with the times.
I think he means from a marketing perspective - the last thing you want tthe real-time commercial side who are most certainly the target audience to think this is a hobby processor for kids like the PickAx is.
That's exactly what I meant. Leave the Blockly stuff for the Toys "R" Us crowd.
Sandy,
In my opinion, that sort of thinking is short sighted. Parallax should do whatever will grow the market share. Hell, the Toys "R" Us crowd has a huge market, and Parallax would be very lucky indeed to end up in there. It could mean millions of units sold per month.
I agree. No reason tools for beginners cannot be provided for the P2. They mostly exist already if I understand correctly, in the P1 versions. So why not?
The Arduino is intended for educational use and novices, that does not stop the AVR being used in millions of "grown up", embedded, industrial applications.
I think millions of units per month might be a bit of a stretch though. The Raspberry Pi has been out for five years, with educational intentions, and has only managed 11 million so far.
I say "only" but I think that is huge.
Arduino is only shipping 10's of thousands of boards a month. I can't find any recent figures on that though.
Yeah, yeah, that is a totally different 'Toys "R" Us' proposition. Which would be nice.
Well, we have toy creators here don't we? What would a toy be that every kid passing through Toys R Us would have to have that can only reasonably be made with a P2?
Perhaps an animatronic unicorn, programmable in blockly. In that sickly fluorescent pink color, to attract the girls that are said to be missing from the robotics scene.
Using a Pi Zero module format would limit the number of exposed I/O, and I'd like all the I/O exposed.
Yes, the P2 would be good for driving parallel LCD panels, however most new panels are LVDS, which (I think) is beyond the streamer/smart pins capabilities.
I think this needs an inexpensive module with all the required voltage regulation (say from 5V), a QSPI flash and a PropPlug connector or on-board USB programming capability. Perhaps 64 pin DIP or DIMM module format.
(sorry I did not see this thread earlier - I've been busy in Pi land)
You did not mention Pi-Zero format for the module ? Wouldn't an existing form factor make more sense than DIP64 ?
With the assorted cheap SBC's I think generating video (except possibly driving LCD's and perhaps VGA) is no longer relevant.
I'd say HDMI Video is outside the P2 target market, but LCD displays with P2 + HyperRAM is looking quite practical.
I see FTDI have a significant business selling a larger module, that is [Touch LCD+Backplane PCB + Plastic Bezel] with mounting for their EVE parts.
Parallax should consider that as well.
However, it seems to me, those that are yelling the hardest for immediate C support (completed last year at the latest) also want it as an official Parallax product and as the central focus of the official IDE (including full debugging support and better throw in simulation too) ... and they'd also prefer Spin not exist at all.
I would like to share some toughts about this matter.
First of all I'm an hobbyst so my point of view may not correspond to the reality, I believe that official support for anything is mandatory for the industry. You can't tell someone that the C compiler is supported by a couple of volunteers that may or may not be available in the future and expect that it uses your chip for big rewarding projects. Don't get me wrong, the work done on PropellerGCC by the volunteers so far was great, but it needs to be officially supported by Parallax in the long term to be desirable by the industry. People like you, me and most of the users on this forum may not care about official support, but that won't be true when you invest hundreds of thousands money in a project.
About Spin... well, I'm one of those that don't like it much, and I think I'll never have continued with the Propeller without C support. Spin resides in rom, unless something changed recently, so it must be completed well before the silicon is fabricated and must be well tested because bugfixes will be nearly impossible afterward. Now, I think that a rom language was useful back when P1 was first developed, considered also the unique processor architecture, but nowadays does it makes sense ? I don't think that any other processor out there has a rom language built in, all compilers will generate assembler code and I believe that P2 should do just that, start executing PASM at the first available location with hubexec, then you can have spin, c, forth, javascript and whatever available as a compiler.
Just my toughts.
The P1 Spin VM resides in ROM. The P2 Spin VM will not. There is no need to finish Spin2 before fabricating the P2 chip.
Absolutely agree David. Unfortunately though, Chip requires Spin2 for his P2 validation programs. I dare say though, it does not need to be a complete Spin2 for his testing (ie not with all bells and whistles).
While P2 continues to add features, many of us are just sitting on the sidelines waiting for a frozen P2 before we invest any time testing the P2. We have wasted so much time over the years on P2.
As I have said many times since P2HOT, I just want a better P1. This could be done in a week by Chip, and while it would no longer be what we all really would like, we would be elated to see a better P1 this year, and, I at least, would then be happier to wait just a little longer for that elusive P2.
Just think about it...
Chip spends 4weeks and takes a few bits from P2 for a better compatible P1...
* P1 compiler compatible (not necessarily binary compatible, but PASM compatible
* 160+ MHz
* maybe 2 clock instructions (dual port COG RAM)
* maybe 2KB LUT (no streamer, just extended cog ram) - requires extended jump/call method or relative jmp/call
* 512KB HUB RAM (1:8 instead of 1:16 access)
* maybe 16 COGs
* possible encryption
* use P2 frame - could this add ADC ?
* 64 I/O
* SPI Flash
Advantages...
* PASM software compatible (require recompile)
* Spin1 compatible, soft (not in ROM), permits faster spin plus later extensions using LUT
* PropGCC C compiler compatible
* BlocklyProp compatible
* Proves the ONSEMI process while yielding a saleable chip that most commercial customers wanted for years
Educational sales enabled the development of the P1 and are doing the same for P2. To be specific: robots, Blockly, educator's courses, supporting teachers, offering a quality product with warranty are all ingredients to Parallax's business model. And yes, the Propeller 1 is at the core of these efforts - especially Blockly!
I understand a point made by Sandy and agree with part of his statement. However (as several pointed out), more than NOT serving a particular customer type, Parallax will need to segment the customer base and speak to BOTH commercial and educational customers on their terms. We have attempted this in the past with Parallax Semiconductor. Eventually we disrupted the Parallax Semiconductor business (with FAEs, a web site, separate phone number) to focus on our educational efforts. The focus (and there can be more than one) will be towards a viable, self-sustaining business of course.
We will soon be looking at what it means to have the P2 as part of our business planning. There will be many productive discussions around this, starting with Chip's vision. In fact, the crowd-sourcing from this exact thread charts the course very clearly. You tell us how to run our business to a large extent, and these pieces become part of our plan. It could be a mix of Spin2, Propeller Expos and a strong user base. Or, it could be a well-funded commercial effort with leadership in specific markets. These pieces are all being discussed.
Love Blockly, if you will. It's really appreciated when the rare educators stumbles into our forums and asks questions. Time and time again you all go out of your way to help that person out. At this moment, Parallax is getting into more classrooms than ever before. And this isn't a confused, viral "gotta have it" kind of thinking where educators buy the latest kit, but a sound, sensible adoption with solid equipment and tutorials. The core attributes our customers report back to us (their words) are features/benefits that simply don't exist with their current hardware. At the core of it is student interest. When students enjoy what they're doing, we ALL win!
Educational customers will expect to grow with all of us when P2 is released. Take a look at what they think about our present system:
I recently attended Parallax’s Blockly Training course and was blown away. As an educator, I always appreciate how thoroughly vetted and documented Parallax material is. It makes is so effortless for an educator to pick up programming and robotics. My students have been introduced into the joy of robotics for over a decade using Parallax robotics kits. In my opinion they are second to none in their thoroughness of teaching: electronics, electricity, wiring, and programming. Their Blockly kits take this to a whole new level! Students can be up and running in no time.
The most difficult part of teaching programming is the first few weeks. This is when many students get frustrated by difficult programming language, and are turned off from programming. The Blockly platform is perfect for teaching programming. Students get instant functionality out of their robots while learning important aspects of programming like variables, frequency, timing, etc. It provides better stepping stones than traditional programming classes.
The beauty of Blockly is that students are programming right from the beginning. Their isn’t the disappointment for students that are poor at typing or have difficulty understanding the logic of programming. With Blockly, they get it right away.
Blockly and Parallax is a perfect combo. The system works so well for differentiated instruction. Struggling students will see results early while picking up programming logic; simultaneously advanced students can toggle back and forth with the C screen to further develop their programming arsenal.
Thank you Parallax for making learning so easy. Every company in the world should do customer support like you do. Parallax actually lays out tutorial sheets for every command and component they utilize. I am not talking techie lingo that doesn’t make any sense either. I am talking clear to follow instructions with examples and explanations. Simply amazing. In addition, when you call the help desk, you get to talk to a real person!
Parallax robots are engaging. I once had a teacher come visit my class during our robotics section and they couldn’t believe how totally engrossed the students were into their robots. They were rushing me to get role done so they could start work, and then rushed off to get their robots, and immediately started working. All without a word from me. This visiting teacher was absolutely amazed.
John Agostinelli
CRANE Coordinator
Engineering Pathways
Mather, CA 95826
Using a Pi Zero module format would limit the number of exposed I/O, and I'd like all the I/O exposed.
If you had read my posts, you would see that adding more pins is a no-brainer.
The PiZero merely gives you a (very) widely used and compatible placement and pinout of one connector, it does not force you to use only one connector.
Can that work? Sounds like cash flow might be an issue here...
It's a possibility, yes.
Crowd funding seems to work best when there are practical, physical near term deliverables.
For P2, that may mean looking at the new Altera Cyclone 10 series, and seeing what P2 subsets that allows, on a compact module that can swap-in for a P2 module.
Smallest ones are sub $7, and 25k LEs is sub $20.
The FT4222H as a low cost QuadSPI/i2c USB bridge, looks well placed to support both P1V and P2 FPGAs
Comments
Did you made any changes at the pad frame layout, specially into the fuses area, and perhaps also had a chance to think about the possibility of having an I/O capability at the Reset signal?
Henrique
Well, it would cost maybe over $100k to do the synthesis required for the full chip test. It would be good to know that the analog is okay before spending that much.
So I think that what Cluso means (and me too) is that it will be a complete waste if you do a shuttle test only for the complete analog outer ring without the inner logic, as you already paid all the 'real state' (7x7 mm, 49mm square).
Latest europractice MPW pricelist says around US $1,400 for each mm square. For 49 mm2, that will mean $68K for a 7*7mm shuttle.
But if the shuttle test is only for a small reduced outer part (left side, or right or top, or bottom side ... or even smaller) then the price of the shuttle can be reduced to $14K (as 10 mm2 is the minimum allowed MPW) and that would make sense.
But not sure, in that reduced shuttle test, if it will server the purpose of completely prove the outer ring.
Some months ago I already though about this idea: Just a side analog die with smartpins and I/O that could be packaged in a narrow DIP-16/18, SOIC-24/28, TSSOP-24/28 with just only between 10/20 pins per side at most.
Four of them can be put on all the sides of a FPGA (top, bottom, left, right). And all together (FPGA + 4x IO ICs sides) over a PCB can simulate a hybrid Propeller.
Then no need to make the inner synthesis.
Think that you will never be able to beat the logic density that current two-digits-nm FPGAs have. When the P2 came to live in the next 3 or 5 years, we probably will have the first single digit nm FPGAs, and the first ARM Cortex MCUs in 22nm FD-SOI process (from ST).
The trouble is that there are maybe 20 internal connections from the core to each pin.
Sorry, the following is a bit out of order, but I am on my iPhone and editing is a bit of a nightmare.
I had thought the outer ring (frame) had worked, and that subsequent changes were minor and without risk. This seems not to be the case???
If you have the time, why is another shuttle run required for testing the frame?
To minimise additional synthesis costs, mIght it be worth putting a P2 2-COG 64KB HUB into the space, with reduced I/O for your special pins?
If it works, then you have some spare chips to send a few to selected testers.
I know I really don't understand the process, but I had thought the frame had been sufficiently verified. Could you mix the testing pins out on port pins, with the mix defaulting to test on power up, and a special P2 instruction to flip them to I/O later. Would even provide software access to test the pins after being proven with your test bed.
It's also one of the reasons I suggested putting an expanded P1 into the frame. As long as some of the frame parts work (digital at least), then you would have a saleable P1 upgrade.
I guess my background just tells me to try and maximise the payback for expenditure, even if it means a little more expenditure.
Are you going to ask about internal FLASH, even it was only for your boot ROM?
There may be some merit in this - if chip design P&R is anything like FPGA & PCB P&R, there is significant time spent in packing a final design, and I have often seen PCBs done on a faster/looser Autoroute setting, in order 'to get something the software guys can start with'.
In this case, you would drop the P2 COGS until P&R was ensured to be very quick.
This less-packed iteration, also gives valuable information on just what can fit along with 16 COGs.
Right now, that 512K memory, is a rather loose, aspirational target, but there may be some hard COGS or MEMORY decisions to make downstream.
Silicon usage would be poorer than a final design, but it does allow more to be tested, including the critical interfaces between Logic and the Custom ring.
Other benefits are final test coverage is better, and testing time is reduced.
I think this would also give a full PLL operation ?
Sounds like that's a conversation you should have had on day one.
The Prop2 is a real time processor in the truest sense of the word. Target real time markets. Machine equipment control isn't real time since the end product is predefined. Great market, but not real time. Process control is real time including the monitoring of tool wear, rocket control and the control of driverless cars. Maybe you should be talking to Elon Musk.
Prop2 will not be an educational 'tool' so NO BLOCKLY!
Sandy
Tom
Sandy,
P2 will be an educational tool, since Parallax is very big on education and everything they make is used for it. Heck even the ELEV8 stuff is... don't see why you would think otherwise.
I think he means from a marketing perspective - the last thing you want tthe real-time commercial side who are most certainly the target audience to think this is a hobby processor for kids like the PickAx is.
Nothing more.
Personally I'm not sold on any Blockley implementation for any micro as a teaching tool. But then again schools seem to want it, so what can you do if you're a vendor except go with the times.
That's exactly what I meant. Leave the Blockly stuff for the Toys "R" Us crowd.
Ken already covered that.
In my opinion, that sort of thinking is short sighted. Parallax should do whatever will grow the market share. Hell, the Toys "R" Us crowd has a huge market, and Parallax would be very lucky indeed to end up in there. It could mean millions of units sold per month.
The Arduino is intended for educational use and novices, that does not stop the AVR being used in millions of "grown up", embedded, industrial applications.
I think millions of units per month might be a bit of a stretch though. The Raspberry Pi has been out for five years, with educational intentions, and has only managed 11 million so far.
I say "only" but I think that is huge.
Arduino is only shipping 10's of thousands of boards a month. I can't find any recent figures on that though.
I was meaning if it was used in a popular Toy sold at Toys "R" Us.
Well, we have toy creators here don't we? What would a toy be that every kid passing through Toys R Us would have to have that can only reasonably be made with a P2?
Perhaps an animatronic unicorn, programmable in blockly. In that sickly fluorescent pink color, to attract the girls that are said to be missing from the robotics scene.
Perhaps an interactive blow up playmate
Yes, the P2 would be good for driving parallel LCD panels, however most new panels are LVDS, which (I think) is beyond the streamer/smart pins capabilities.
However I do need P2 chips first...
- kill the P2 (would cost too much to make P1+ and P2 at this time)
- be a LOT lower performance than P1
I grant you that for your uses it would be enough, but it would not be for half of my potential uses... I need the ADC's and much higher cog speeds.
Educational sales enabled the development of the P1 and are doing the same for P2. To be specific: robots, Blockly, educator's courses, supporting teachers, offering a quality product with warranty are all ingredients to Parallax's business model. And yes, the Propeller 1 is at the core of these efforts - especially Blockly!
I understand a point made by Sandy and agree with part of his statement. However (as several pointed out), more than NOT serving a particular customer type, Parallax will need to segment the customer base and speak to BOTH commercial and educational customers on their terms. We have attempted this in the past with Parallax Semiconductor. Eventually we disrupted the Parallax Semiconductor business (with FAEs, a web site, separate phone number) to focus on our educational efforts. The focus (and there can be more than one) will be towards a viable, self-sustaining business of course.
We will soon be looking at what it means to have the P2 as part of our business planning. There will be many productive discussions around this, starting with Chip's vision. In fact, the crowd-sourcing from this exact thread charts the course very clearly. You tell us how to run our business to a large extent, and these pieces become part of our plan. It could be a mix of Spin2, Propeller Expos and a strong user base. Or, it could be a well-funded commercial effort with leadership in specific markets. These pieces are all being discussed.
Love Blockly, if you will. It's really appreciated when the rare educators stumbles into our forums and asks questions. Time and time again you all go out of your way to help that person out. At this moment, Parallax is getting into more classrooms than ever before. And this isn't a confused, viral "gotta have it" kind of thinking where educators buy the latest kit, but a sound, sensible adoption with solid equipment and tutorials. The core attributes our customers report back to us (their words) are features/benefits that simply don't exist with their current hardware. At the core of it is student interest. When students enjoy what they're doing, we ALL win!
Educational customers will expect to grow with all of us when P2 is released. Take a look at what they think about our present system:
The most difficult part of teaching programming is the first few weeks. This is when many students get frustrated by difficult programming language, and are turned off from programming. The Blockly platform is perfect for teaching programming. Students get instant functionality out of their robots while learning important aspects of programming like variables, frequency, timing, etc. It provides better stepping stones than traditional programming classes.
The beauty of Blockly is that students are programming right from the beginning. Their isn’t the disappointment for students that are poor at typing or have difficulty understanding the logic of programming. With Blockly, they get it right away.
Blockly and Parallax is a perfect combo. The system works so well for differentiated instruction. Struggling students will see results early while picking up programming logic; simultaneously advanced students can toggle back and forth with the C screen to further develop their programming arsenal.
Thank you Parallax for making learning so easy. Every company in the world should do customer support like you do. Parallax actually lays out tutorial sheets for every command and component they utilize. I am not talking techie lingo that doesn’t make any sense either. I am talking clear to follow instructions with examples and explanations. Simply amazing. In addition, when you call the help desk, you get to talk to a real person!
Parallax robots are engaging. I once had a teacher come visit my class during our robotics section and they couldn’t believe how totally engrossed the students were into their robots. They were rushing me to get role done so they could start work, and then rushed off to get their robots, and immediately started working. All without a word from me. This visiting teacher was absolutely amazed.
John Agostinelli
CRANE Coordinator
Engineering Pathways
Mather, CA 95826
Ken Gracey
The PiZero merely gives you a (very) widely used and compatible placement and pinout of one connector, it does not force you to use only one connector.
Can that work? Sounds like cash flow might be an issue here...
It's a possibility, yes.
For P2, that may mean looking at the new Altera Cyclone 10 series, and seeing what P2 subsets that allows, on a compact module that can swap-in for a P2 module.
Smallest ones are sub $7, and 25k LEs is sub $20.
The FT4222H as a low cost QuadSPI/i2c USB bridge, looks well placed to support both P1V and P2 FPGAs