You're right, radiation is probably the main way it releases heat.
But, with tiny vias it has to go through the vias to get to the ground plane.
With giant vias, it can radiate directly and also have great thermal contact to ground plane.
I have some finite element software that could evaluate this.
Probably easier just to try it though...
That also depends on paste wicking and number of planes.
The Eval board has very small vias, and they look closed at bottom, with solder mask, so expect not much wicking, but that is 4L board, so the plane is quite close.
We have used larger vias with paste, on some boards for higher current and thermal vias, and we have also used vias under D2PAK parts, that nicely wick solder paste.
Giant vias may be ok for manual soldering, but maybe a mid-size via, that has solder mask clearance on bottom and is designed to wick, combined with a 100% paste coverage, can give the best volume production thermal outcome ?
The idea of having some big vias exposed to solder at the thermal pad contact area, in order to ease hand soldering is pretty good.
In order to avoid excess solder paste to flow laterally, during heat-up, causing bridges and shorts along the 100-pin lead frame inner perimeter, it's advisable to surround the exposed metal area, at pcb top surface, within four lines of 0.3 mm vias, linearly spaced 1.2 - 1.4 mm apart from each other.
This way, when the solder paste melts and spreads between lqfp package exposed pad and the land pattern, those perimeter vias can act as fiducials, showing, due solder wicking thru their tubes, that moltem solder has reached that far.
Otherwise, it would be very dificult to visually inspect the finished product, looking for poor solder connections and voids at the interface area.
I couldn't fine any examples of anybody using big vias under thermal pads, so it's probably a bad idea...
But, I'm toying with the idea anyway...
I just put a P2 together in Eagle and here's what it looks like with the largest vias that Eagle comes with (3.2 mm).
Funny how this chip isn't all that much bigger than P1 (top center of image).
Pentalogix says they can do plated vias up to about 1/4", ~6mm. But, they said they can do bigger with "plated internal route".
I'm not exactly sure what they meant by that...
Would be great if I could make an about full size of pad square and have the edge plated...
We've used a single big plated hole with the MAX10 FPGAs exposed pad, which is similar size. It works fine. The diameter of the hole is around 5mm, which allows the soldering iron tip to get into the corner quite easily. I'm not really sure of the advantage of the five medium sized holes vs one large one (perhaps with fine vias around the rest of the pad)
Pentalogix says they can do plated vias up to about 1/4", ~6mm. But, they said they can do bigger with "plated internal route".
I'm not exactly sure what they meant by that...
...
I think they mean they can drill to 6mm, and above that they route a circular slot aka 'make a larger hole' with a router and then plate that internal route.
I've found a video from some guy doing WQFN48 hand soldering that could eventually be a good solution...
Wow, he really goops on the flux!
-Phil
Yeah, though, long ago, I had a partner who was an specialist at Sega game simulators, many-DSP controller boards repair. He used to do the same thing and, during our association (~17 years long) he was ever succesfull healing those beasts.
Comments
There was a lot of discussions about that subject at the P2D2 - An open hardware reference design for the P2 CPU thread.
https://forums.parallax.com/discussion/168645/p2d2-an-open-hardware-reference-design-for-the-p2-cpu/p1
The idea of having some big vias exposed to solder at the thermal pad contact area, in order to ease hand soldering is pretty good.
In order to avoid excess solder paste to flow laterally, during heat-up, causing bridges and shorts along the 100-pin lead frame inner perimeter, it's advisable to surround the exposed metal area, at pcb top surface, within four lines of 0.3 mm vias, linearly spaced 1.2 - 1.4 mm apart from each other.
This way, when the solder paste melts and spreads between lqfp package exposed pad and the land pattern, those perimeter vias can act as fiducials, showing, due solder wicking thru their tubes, that moltem solder has reached that far.
Otherwise, it would be very dificult to visually inspect the finished product, looking for poor solder connections and voids at the interface area.
But, I'm toying with the idea anyway...
I just put a P2 together in Eagle and here's what it looks like with the largest vias that Eagle comes with (3.2 mm).
Funny how this chip isn't all that much bigger than P1 (top center of image).
I've found a video from some guy doing WQFN48 hand soldering that could eventually be a good solution...
https://youtube.com/watch?v=BvhE16vBfX4
P.S. too early... too expectancy... too bad...
the thermal pad wasn't soldered anyway... :frown:
I'm not exactly sure what they meant by that...
Would be great if I could make an about full size of pad square and have the edge plated...
-Phil
Yeah, though, long ago, I had a partner who was an specialist at Sega game simulators, many-DSP controller boards repair. He used to do the same thing and, during our association (~17 years long) he was ever succesfull healing those beasts.
Good solder joints need clean copper, and lots of flux makes for clean copper.