For P3 I want just want a faster P1 with PortB (64 pins), some smartpins, eeprom or flash, and at less than US $1.
Nice wish-list, but already you have jumped way off the industry price curve.
If you look at the prices I posted above, the cheapest 100pin part (78io) from any supplier, is $1.75, the next 3 average around $2.15
Then they don't need the P3, they can just start buying any recent low cost FPGA (like Max 10, Cyclone 10 LP, or ICE40) with embedded RAM, internal DDR3 controller, multipliers, ADC, and on and on ... starting from around $2 to $30.
That's a valid point, and the iCE40 has a new member with 128kBytes RAM, and QFN48, 5280 LE which makes a somewhat practical MCU host.
The 39 io will cost just under $7, so you need two, to meet 64io requirement.
Still a l-o-n-g way from that imagined "at less than US $1."
Parallax certainly could do a module using ICE40UP5K-SG48 (or similar), as once you sell a module, the exact silicon BOM matters less.
Their FLiP form factor seems a good start, you could fit a 39io QFN48 on there, and not lose user IO for comms or flash loader.
There would also be room to add a 22c MCU for ADC,PWM,FIFO'd UART etc
BTW
Max10M02 wont fit any form of P1.
10M04 will fit a 1 cog P1 with counters, video removed and I/o stripped down. (Lengthy Quartus wrestle involved)
10M08 fits 3 cogs Ok.
BTW
Max10M02 wont fit any form of P1.
10M04 will fit a 1 cog P1 with counters, video removed and I/o stripped down. (Lengthy Quartus wrestle involved)
10M08 fits 3 cogs Ok.
Ok, rather discounts the 10M02, and the 10M08 looks to have a place, given :
To use a chip with the capabilities of the P2, 16 cores, smart pins etc, I would be willing to pay more, really. But then that might limit where I could use it, and it might turn away new interest too. Parallax will not make their money back from education or hobby sales, if that's all they had then they would have to sell P2 for $100 and still take a risk. The low price is a risk but also a necessity if it is to attract volume use. There is however the possibility that volume use will be on a variant of the P2, the "P2 family" so to speak.
The new top of the line ARM cortex M7 STM32H743VGT6 at 400mhz (40 nm chip-fabrication process) coming soon
1MB Flash and 1MB SRAM in a 100-pin LQPF100 package starts at budgetary pricing of $8.17 for orders of 10,000 pieces.
But I think the P2 could beat it at some applications, though need external memory.
The new top of the line ARM cortex M7 STM32H743VGT6 at 400mhz (40 nm chip-fabrication process) coming soon
1MB Flash and 1MB SRAM in a 100-pin LQPF100 package starts at budgetary pricing of $8.17 for orders of 10,000 pieces.
But I think the P2 could beat it at some applications, though need external memory.
How many wait states for that 400MHz ?
The 'really big' ARMs are less of a threat to P2, as it can sit alongside one to give a real-time boost.
A Max 10 10M02 is never going to do what a P1 does!!!
That is an interesting statement.
As far as I can tell a typical Propeller application consists of a "main" program in Spin. Which uses a bunch of peripherals, UART, SPI, I2C, VGA, etc, which are created in software running on other COGs. Perhaps part Spin part PASM. Perhaps including some weird interface that requires custom "bit banging" in PASM.
That is great. Get a Propeller, write the code, job done.
But today, all of a sudden FPGAs are getting really cheap. You can throw in a CPU core to do you "main" program. You can surround it with whatever peripherals you like. Written in Verilog instead of PASM.
I have no idea about the Max 10 but this is already possible with 10 dollar Lattice devices. With Open Source tools to boot.
The whole multi-core concept of the Propeller is up against some serious competition now.
If I understand correctly not many people are going to be using a raw P2 either. They will be buying a board with it on.
Maybe I missed a point about the 10M02 but a quick google told me it's big enough to hold a processor core with room to spare for whatever logic you want to put around it.
Exactly the territory the P1 and P2 cover.
The question for a prospective user then is "Do I write verilog or do I write PASM to get what I want?"
If I understand correctly not many people are going to be using a raw P2 either. They will be buying a board with it on.
Maybe I missed a point about the 10M02 but a quick google told me it's big enough to hold a processor core with room to spare for whatever logic you want to put around it.
Exactly the territory the P1 and P2 cover.
The question for a prospective user then is "Do I write verilog or do I write PASM to get what I want?"
I think competition is getting stiff.
I think you mean "not many hobbyists" are going to use a raw P2 either. However I'd say over 99% of the sales will be production. Remember, you can have 1,000 people buy "a P2" while one customer in one purchase uses 1,000 just for preproduction. Parallax though are interested in supporting the education market and they will make their money out of production P2s and also out of their own P2 production where you the education market doesn't mind paying a premium for their boards and bots.
A Max 10 10M02 is never going to do what a P1 does!!!
That is an interesting statement.
As far as I can tell a typical Propeller application consists of a "main" program in Spin. Which uses a bunch of peripherals, UART, SPI, I2C, VGA, etc, which are created in software running on other COGs. Perhaps part Spin part PASM. Perhaps including some weird interface that requires custom "bit banging" in PASM.
That is great. Get a Propeller, write the code, job done.
But today, all of a sudden FPGAs are getting really cheap. You can throw in a CPU core to do you "main" program. You can surround it with whatever peripherals you like. Written in Verilog instead of PASM.
I have no idea about the Max 10 but this is already possible with 10 dollar Lattice devices. With Open Source tools to boot.
The whole multi-core concept of the Propeller is up against some serious competition now.
Lately I've been playing with a Cypress PSoC chip. It's a combination of an ARM and some programmable logic. It also has on-board Bluetooth. I think the chip is a few dollars. It's only a Cortex M0 though.
If I understand correctly not many people are going to be using a raw P2 either. They will be buying a board with it on.
Maybe I missed a point about the 10M02 but a quick google told me it's big enough to hold a processor core with room to spare for whatever logic you want to put around it.
Exactly the territory the P1 and P2 cover.
The question for a prospective user then is "Do I write verilog or do I write PASM to get what I want?"
I think competition is getting stiff.
I think it's also possible to compile C into hardware so maybe knowing Verilog isn't required?
An L1 cache, STM32H7 devices deliver the maximum theoretical performance of the Cortex-M7 core,
regardless if code is executed from embedded Flash or external memory: 2020 CoreMark /856 DMIPS at 400 MHz.
16 Kbytes +16 Kbytes of I-cache and D-cache.
192 Kbytes of TCM RAM (including 64 Kbytes of ITCM RAM and 128 Kbytes of DTCM RAM for time-critical routines and data.
This chip will bridge the not-so-realtime raspberry and arm cortex's, this IC doubles the speed of the last top-of-the-line ST had.
At a price of $13/each at a ~1000, not that cheap.
I think the P2 with external hyperram/flash could compete if that combo comes in at the same price.
I donno - it depends. For my self I design high end electronics products, clocks, scoreboards, instrumentation & industrial control systems. So the Project Board USB, Prop Mini, and new FLiP module are what I use exclusively. I don't have time to re-engineer, trouble shoot and get into production something that already works are perfect for me, no fuss, no muss and they work every time. I spend a lot more time in developing custom software, PCB, and enclosures, add in User manuals, sales promotions, Web site, the list goes on. It is well over X100 times what the P1 (or P2) chip would cost.
IF I was making cell phones, or some other mass consumer electronics - Yes the chip cost would be a major factor in the decision making. We would be talking 100K, to maybe several Million units. Even given that, I would still consider the ease of software development and the chip count in the final PCB, ease of manufacture, and reliability.
Comments
Nice wish-list, but already you have jumped way off the industry price curve.
If you look at the prices I posted above, the cheapest 100pin part (78io) from any supplier, is $1.75, the next 3 average around $2.15
I can't find a 10M02 for $2.00/100 ?
Digikey say $3.02@ 100, for 3x3 BGA36 with 27io and 2K LE and 13kB RAM => That's $7.15 on a per-IO basis.
That's a valid point, and the iCE40 has a new member with 128kBytes RAM, and QFN48, 5280 LE which makes a somewhat practical MCU host.
The 39 io will cost just under $7, so you need two, to meet 64io requirement.
Still a l-o-n-g way from that imagined "at less than US $1."
Parallax certainly could do a module using ICE40UP5K-SG48 (or similar), as once you sell a module, the exact silicon BOM matters less.
Their FLiP form factor seems a good start, you could fit a 39io QFN48 on there, and not lose user IO for comms or flash loader.
There would also be room to add a 22c MCU for ADC,PWM,FIFO'd UART etc
Max10M02 wont fit any form of P1.
10M04 will fit a 1 cog P1 with counters, video removed and I/o stripped down. (Lengthy Quartus wrestle involved)
10M08 fits 3 cogs Ok.
10M08SCU169C8G $8.37 @ 1000 8000LE 130io 387072b (48384 Bytes) 2.85V ~ 3.465V 169-UBGA (11x11)
So if you really need a ship-load of I/O connected to up to 3 COGs, that stacks up ok.
(Not the most friendly package)
Seriously though... Parallax really only needs one customer, let's just hope They insist on 28nm:)
And we all know who "They" are/is.
MAGA
1MB Flash and 1MB SRAM in a 100-pin LQPF100 package starts at budgetary pricing of $8.17 for orders of 10,000 pieces.
But I think the P2 could beat it at some applications, though need external memory.
The 'really big' ARMs are less of a threat to P2, as it can sit alongside one to give a real-time boost.
As far as I can tell a typical Propeller application consists of a "main" program in Spin. Which uses a bunch of peripherals, UART, SPI, I2C, VGA, etc, which are created in software running on other COGs. Perhaps part Spin part PASM. Perhaps including some weird interface that requires custom "bit banging" in PASM.
That is great. Get a Propeller, write the code, job done.
But today, all of a sudden FPGAs are getting really cheap. You can throw in a CPU core to do you "main" program. You can surround it with whatever peripherals you like. Written in Verilog instead of PASM.
I have no idea about the Max 10 but this is already possible with 10 dollar Lattice devices. With Open Source tools to boot.
The whole multi-core concept of the Propeller is up against some serious competition now.
While these cheap FPGA's are nice, their packaging can be a real downer.
3 x 3mm 36 pin BGA's for example...Yikes!
If I understand correctly not many people are going to be using a raw P2 either. They will be buying a board with it on.
Maybe I missed a point about the 10M02 but a quick google told me it's big enough to hold a processor core with room to spare for whatever logic you want to put around it.
Exactly the territory the P1 and P2 cover.
The question for a prospective user then is "Do I write verilog or do I write PASM to get what I want?"
I think competition is getting stiff.
I think you mean "not many hobbyists" are going to use a raw P2 either. However I'd say over 99% of the sales will be production. Remember, you can have 1,000 people buy "a P2" while one customer in one purchase uses 1,000 just for preproduction. Parallax though are interested in supporting the education market and they will make their money out of production P2s and also out of their own P2 production where you the education market doesn't mind paying a premium for their boards and bots.
An L1 cache, STM32H7 devices deliver the maximum theoretical performance of the Cortex-M7 core,
regardless if code is executed from embedded Flash or external memory: 2020 CoreMark /856 DMIPS at 400 MHz.
16 Kbytes +16 Kbytes of I-cache and D-cache.
192 Kbytes of TCM RAM (including 64 Kbytes of ITCM RAM and 128 Kbytes of DTCM RAM for time-critical routines and data.
This chip will bridge the not-so-realtime raspberry and arm cortex's, this IC doubles the speed of the last top-of-the-line ST had.
At a price of $13/each at a ~1000, not that cheap.
I think the P2 with external hyperram/flash could compete if that combo comes in at the same price.
IF I was making cell phones, or some other mass consumer electronics - Yes the chip cost would be a major factor in the decision making. We would be talking 100K, to maybe several Million units. Even given that, I would still consider the ease of software development and the chip count in the final PCB, ease of manufacture, and reliability.