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Smart Pins Docs and features

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  • @evanh

    For now on the scope while I am learning the pins. For right now the pins are my challenge.
    Thanks
  • @evanh

    The example that you gave was a lot of help on many fronts, including the hubset.
    Please a little more detail on this:
    wxpin ##$2_2800,#56 'frame period (2) and base period ($2800)

    Frame period and base period. I will look up on google and see.
    Thanks
  • Peter JakackiPeter Jakacki Posts: 10,193
    edited 2019-07-21 01:58
    @pilot0315 - Using TAQOZ to test smartpin modes is about as hard as typing in a command line in DOS or Linux. The good thing is that there is no special "has to be right" syntax. Typing 16 PIN 100 KHZ after which anytime you can type 125,500 HZ to change the frequency if you have not selected another pin.
    Try 5 100 1 PWM which will switch the selected PIN to 5/100 or 5% PWM mode with a clock divider of 1. Don't just act ........ interact

    Generating 3 pulses that are 5 clocks high and 20 clocks low is easy too although you will need a scope to see it:
    5 20 HILO   3 PULSES
    
    Thereafter you can say 10 pulses without having to setup the hi/lo ratio again. This is the section dealing with it in the TAQOZ online document.

    To output 1V on pin 16 is simple too as this sets up the pin as a DAC and scales the user input. This one you can check with a meter.
    16 PIN 1.00 V
    
    Since you can interact, you can just type this in to the "command line' so next line you could type 2.50 V to set it to 2.5V (use 2 decimal places to keep the scaling correct).
    1356 x 443 - 133K
  • evanhevanh Posts: 15,091
    edited 2019-07-21 01:01
    You'll want to be using a DAC output then. First step is to turn on a DAC and test it.
    con
    	DACLEVEL	= 222
    
    
    dat	org
    
    	hubset	#1			'rcslow
    
    	wrpin	##(%10100<<16)|(DACLEVEL<<8), #56	'custom pin config:  DAC_MODE
    	dirh	#56					'DAC enable
    
    .loop
    	jmp	#.loop			' keep cog running to hold DIR on
    
    


    And here's the now much reposted DAC_MODE configuration details:
    WRPIN   {#}D,{#}S	Write D to mode register of smart pin S[5:0], acknowledge smart pin.
    
       bit 30    25     20   15   10      5     0
            |     |      |    |    |      |     |
    D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0
    
     2    1    1
     0    5    0
    %PPPPPPPPPPPPP: low-level custom pin control
    
    
    	 0      5    0
    	%101_VV_DDDDDDDD = DAC_MODE (%TT = 00 and %MMMMM = 00000), 8-bit flash
    		OUT enables PinA ADC (ADC config %011), sysclocked bitstream on IN
    		DIR enables PinA DAC output
    		%VV = PinA DAC config
    			00: 990 ohm, 3.3 volt range
    			01: 600 ohm, 2.0 volt range
    			10: 123.75 ohm, 3.3 volt range
    			11: 75 ohm, 2.0 volt range
    		%DDDDDDDD = DAC level
    
    		for %TT = %01 and %MMMMM = %00000, %101_VV_xxxxSSSS = COG_DAC mode
    			%SSSS = Cog/streamer select: sets DAC level (registered?)
    
    		for %00000 < %MMMMM < %00100 = SMART_DAC mode
    			DIR/IN are usual smartpin ctrl
    			%DDDDDDDD ignored, smartpin sets DAC level (registered?)
    
    		for %MMMMM >= %00100 or (%TT = %1x and %MMMMM = %00000) = BIT_DAC mode
    			OUT sets DAC level (clocked?, ADC disabled?, IN = ?)
    				0: 0 = GIO level
    				1: %DDDDDDDD
    
    
  • evanhevanh Posts: 15,091
    edited 2019-07-21 01:28
    Next step has a choice. You can carry on loading the DAC level using WRPIN, or use SETDACS instruction, or use a smartpin. Or even use a streamer! In this example I'll use SETDACS.
    dat		org
    		hubset	#1			'rcslow
    		wrpin	##(%10100<<16)|(%000001<<6), #56	'custom pin config:  DAC_MODE/COG_DAC, pin56 mapped to cog0
    		dirh	#56					'DAC enable
    
    .loop
    		add	daclevel, #1		' do a sawtooth from the 8-bit rollover
    		setdacs	daclevel		' pin56 maps to lowest 8 bits of daclevel, pin57 can map to bits[15..8], up to pin59
    		jmp	#.loop			' keep cog running to hold DIR on
    
    
    daclevel	long	222
    
    

    EDIT: In the pin56 setup WRPIN, I've hard coded for cog0 mapping. If wanting to make this adaptable for any cog then would need to get the cog ID and use that. Eg:
    		cogid	pa
    		shl	pa, #8
    		or	pa, ##(%10100<<16)|(%01<<6)	'custom pin config:  DAC_MODE/COG_DAC, pin56 mapped to this cog
    		wrpin	pa, #56
    		...
    
  • evanhevanh Posts: 15,091
    This time using a smartpin:
    dat		org
    		hubset	#0			'rcfast
    		dirl	#56
    		wrpin	##(%10100<<16)+(%01<<6)+%00011_0, #56	'custom pin config:  DAC_MODE, DIR on, smartpin PWM DAC dither
    		wxpin	#256, #56			'PWM period is multiples of 256 to emulate extended 8 bits
    		dirh	#56				'smartpin enable
    
    .loop
    		add	daclevel, #1		' do a sawtooth with 16-bit rollover
    		wypin	daclevel, #56
    		waitx	#30			' pause for visual effect on the LED
    		jmp	#.loop
    
    
    daclevel	long	222
    
  • evanhevanh Posts: 15,091
    edited 2019-07-21 04:15
    Note that bit 6 of the pin config (%TT = %01) is set on in both those examples. Its meaning changes depending on whether a smartpin is in use or not:
    - When used with SETDACS the smartpin was off, so the meaning then is that it selects COG_DAC pin mode.
    - When the smartpin is active, then the meaning is that it forces on the pin's DIR control.

  • @"Peter Jakacki"
    Arrette!!! Suis'je pas interesser avec votre language qui s'appelle "TAQOZ" a cette instant.
    Si j'ai des questions qui concerne "TAQOZ" dans le future, J'envoi un message a toi dans le future.
    Mes concernes sont avec: P2ASM, P1ASM, C++, PROPC, SPIN ET PASCAL.
    Merci
  • @evanh
    Thanks. I will try this.
  • @evanh
    I assume thet the led on pin 56 is supposed to blink or something. Nothing there using the first bit of code. I changed the pin to pin 0 and even added:
    testp #0 wc 'get pin state
    drvc #1

    got nothing. Am going to try the next bit of code. Good thing is that I understand more.
  • @pilot0315, Even if you have no interest in TAQOZ at the moment, telling Peter to stop is an inferior approach when viewed from a community perspective. If Peter’s input is unhelpful for you, you can always choose to not read it. Others may benefit from the examples offered by Peter (I do), and if later you choose to allow yourself an interest in doing this type of thing using Forth you could come back and read them rather than asking the questions then.
    Peter is not being paid to partake in the forum and if his contribution is met with short dismissive comments often enough he may choose to withdraw. That would be a great loss IMHO.
  • pilot0315 wrote: »
    @"Peter Jakacki"
    .....................
    Merci

    FInally, finally, a thank you for all my effort despite the totally free and open nature of it, asking nothing in return.
    It's not something I get very often despite the help with ultra simple examples like 16 PIN 1.00V to setup a pin as a DAC to output 1V.

    BTW,
    Cambridge definition of the word "forum" as in "Parallax Forum":
    a situation or meeting in which people can talk about a problem or matter especially of public interest:

    a forum for debate/discussion


    Forums are public, not private as in just one person, and debate/discussion implies more than one way of looking at it, otherwise there is no need for discussion. The one asking for help and receiving it can decide which help they will apply and a thank-you is an optional courtesy. This Parallax forum is "gold class" because it has always maintained a high level of courtesy and respect with informative, accurate, diverse, and useful feedback unlike most other forums today. Let's keep it that way.


  • evanhevanh Posts: 15,091
    edited 2019-07-22 02:17
    pilot0315 wrote: »
    I assume thet the led on pin 56 is supposed to blink or something. Nothing there using the first bit of code.
    Not the first one. It's just a static level of 222 (0-255) which equates to a high. The LED driver needs a low to activate the LED.

    EDIT: It was for the scope. If you edit the DACLEVEL and rerun you'll get different voltages on the scope.

  • @AJL

    I will simply ignore him. I felt pressured by him trying to force his code on me.
    I am confused enough, don't need extra confusion.
    Thanks you for your support.
  • Peter JakackiPeter Jakacki Posts: 10,193
    edited 2019-07-24 01:25
    @pilot0315 Don't be so rude to those who take the time and effort to offer help which very strangely you interpret as pressure and forcing.
    I normally don't take things personally but I take great exception to your insults as there was no need to say what you just said about me while thanking them for "counselling" you about me. No one might know if you like coffee or tea, but they are being courteous by offering you both.
  • @"Peter Jakacki"
    I am not being rude. I am only concerned with the code languages that I want to be concerned with. Please, you may be a good coder and programmer but I am only concerned with certain languages. So I ask you again gently that is why I changed languages, Lassaiez moi tranquille, mon ami, pa

  • @"Peter Jakacki"

    I am not attempting to be rude. I just am concentrating on p2asm, spin and C. I cannot introduce anything else right now. Please understand.
  • @pilot0315 Sorry, I thought this was a public forum and this wasn't even your thread. Don't you realize that the information provided here is for everyone, not just you, or do you speak for everyone??? Weeks, months, even years from now others can be reading this thread and finding the answer that they need, which may not be the one that you were seeking. If you start a thread and someone is being rude or negative, then complain to the moderators. But to be rude because you are not interested is just being rude.
  • pilot0315 wrote: »
    @"Peter Jakacki"
    Arrette!!! Suis'je pas interesser avec votre language qui s'appelle "TAQOZ" a cette instant.
    Si j'ai des questions qui concerne "TAQOZ" dans le future, J'envoi un message a toi dans le future.
    Mes concernes sont avec: P2ASM, P1ASM, C++, PROPC, SPIN ET PASCAL.
    Merci
    First things first, I can understand French, and you are being rude, IMHO. Even if you didn't want to pass off at that, asking for someone to STOP is not correct, especially when that someone is contributing to the forum in a positive way. That behavior doesn't age well here, or anywhere else, for that matter. Also, only one person here provided feedback, and you still do not seem to be convinced, so here I am providing feedback to you, too.

    Although TAQOZ might not be of interest to you, it is of interest to others, me included. It is a great diagnostics tool (as far as I can perceive it) that allows you to interact and test the P2 without any special software or compilers. And yes, this is important at this stage, because the compilers are still a work in progress.

    Last thing, do you like me to type in Portuguese in this forum? I know I wouldn't. Please, use the language that everyone else uses. So we can understand each other.

    Kind regards, Samuel Lourenço
  • samuellsamuell Posts: 554
    edited 2019-07-24 15:37
    Now back to topic!

    Speaking of smart pins, I think the datasheet should provide a block diagram for each pin, or set of pins. I'm more of a visual kind of person, and a diagram would certainly go a long way for me. Is it possible?

    I'm thinking something in the lines of the block diagram on the AD9834 datasheet, for example. Registers as inputs and sets of pins in the "output" side, with all the DACs and ADCs, selectors and logic in the middle. Doesn't need to be an exact representation of the silicon, of course (nor I would ever ask that, since it sure breaks Parallax IP). A set of functional blocks would do for me.

    Kind regards, Samuel Lourenço
  • Back on topic, @evanh did an ASCII block diagram which I started to do a proper drawing for it the other day. It looks good so far and I just need to finish it and add it to "the" datasheet (the one I did up).
  • Back on topic, @evanh did an ASCII block diagram which I started to do a proper drawing for it the other day. It looks good so far and I just need to finish it and add it to "the" datasheet (the one I did up).
    Thanks Peter! That would be great. It would be a great addition to the datashort, since it would cover the nuances and clear the doubts.

    Kind regards, Samuel Lourenço
  • jmgjmg Posts: 15,140
    edited 2019-07-24 20:38
    samuell wrote: »
    Although TAQOZ might not be of interest to you, it is of interest to others, me included. It is a great diagnostics tool (as far as I can perceive it) that allows you to interact and test the P2 without any special software or compilers. And yes, this is important at this stage, because the compilers are still a work in progress.

    Yes, TAQOZ is very nifty for test verification.

    samuell wrote: »
    Speaking of smart pins, I think the datasheet should provide a block diagram for each pin, or set of pins. I'm more of a visual kind of person, and a diagram would certainly go a long way for me. Is it possible?..Registers as inputs and sets of pins in the "output" side, with all the DACs and ADCs, selectors and logic in the middle

    That certainly helps show what the pin cells contain, but I think the Smart pin modes are too terse in the DOCs, so those modes need expanding & a block diagram is too coarse...

    Ideally, that expansion should be in the form of equations and working code snippets, that show the access to each mode.

    I'm not sure TAQOZ supports all PIN modes and some of the examples are great, but are actually too encapsulated
    eg
    16 PIN 1.00V DAC -> 1.00V
    5 100 1 PWM Selected PIN to 5/100 or 5% PWM mode with a clock divider of 1
    that's impressive, & powerful, but it does not expose the register accesses needed, which is what is missing.

    Other vendors have Configuration Wizards, but they can get tricky if you want to modify your settings later. (many are write only)

    evanh's example above is good, but has many magic constants, and the column tags in the expanded mode do not line up with the shifts applied here.
    	wrpin	##(%10100<<16)|(DACLEVEL<<8), #56	'custom pin config:  DAC_MODE
    	dirh	#56					'DAC enable
    

    to me, better is less magic constants along the lines of this, which also tags columns by the shifts needed (which coders need to know) rather than a decimal marker (which they do not need)
    
    WRPIN   {#}D,{#}S       Write D to mode register of smart pin S[5:0], acknowledge smart pin.
    
       bit   28   24   21            8  6     1 0
              |    |   |             |  |     |
    D/# = %AAAA_BBBB_FFF_PPPPPPPPPPPPP_TT_MMMMM_0
    
                        %PPPPPPPPPPPPP: low-level custom pin control expanded 
                         1  1        0
                         8  6        8
                      %101_VV_DDDDDDDD = DAC_MODE (%TT = 00 and %MMMMM = 00000), 8-bit flash
                              OUT enables PinA ADC (ADC config %011), sysclocked bitstream on IN
                              DIR enables PinA DAC output
                              %VV = PinA DAC config
                                      00: 990 ohm, 3.3 volt range
                                      01: 600 ohm, 2.0 volt range
                                      10: 123.75 ohm, 3.3 volt range
                                      11: 75 ohm, 2.0 volt range
                              %DDDDDDDD = DAC level
    <snip unused for now>
    
    then that bit mapped information expands to some mode defines like
    con
            DAC_MODE        = %101 << 18
             DAC_990_3v3    = (%00  << 16) | DAC_MODE
             DAC_600_2v0    = (%01  << 16) | DAC_MODE
             DAC_124_3v3    = (%10  << 16) | DAC_MODE
             DAC_75_2v0     = (%11  << 16) | DAC_MODE
            DAC_SHL         = 8 
    

    and then the user applies those
    con
            DACLEVEL        = 222
            DAC_P56   = 56        
    dat ..
            wrpin   ##(DAC_990_3v3 | (DACLEVEL << DAC_SHL)), #DAC_P56       'custom pin config:  DAC_MODE
            dirh    #DAC_P56                                     'DAC enable
    

    With this, someone with a Editor with a Find Declaration button, can hover over the DAC_990_3v3, and find the other possible DAC modes (Usually in an include file), and it self-documents better.

    Maybe that is then clear enough for new users to feel confident moving pins, or changing DAC modes ?

  • @everybody

    I am no attempting to start any discord among us. Peter is a nice guy from what I see as all of you are. I just want to stay with what I am learning with all your help. I appreciate all of you and Peter for all of your expertice and experience. I just wanted to not have examples sent to me in another language that I would have to learn from scratch.
    As I posted earlier no wars please. I know that many of you have more experience in asm of any type than me. I am re-learning asm after 30 years having been exposed to it early in college. That was a bad class for me. I dropped the class due to an extremely personal reason.
    Came back to coding 10 years ago. Due to parallax I have so much enjoyed my own personal SODUKU. This my hobby and I have learned stuff beyond my dreams about stuff that did not exist when I was a kid and and college originally.
    To Peter, I used French so in my mind to soften my response to the stuff you were sending me in a code language that I did not understand and directly to my questions to code that I understand.
    Your code en tous ca is great but it does not help me at this time. To all I WAS NOT ASKING HIM TO STOP IN THE FORUM, Just directly to my questions. Wanting only suggestions in p2asm.
    To everybody I thank you for your patience with my neophyte code understanding of assembly language.
    So let us please put this to bed.
    Thank you.
    Let's start fresh.

    Martin

    fyi Samuel Lourenço I can read your comments in your code in portugese. Taught me a lot about your language I was very suprised at my level of understanding. I will send you a private message about my language education. I really enjoyed the portugese connection Thank you
    Thank you. Was fun.
  • cheezuscheezus Posts: 295
    edited 2019-07-25 07:01
    Could someone point me to some PASM examples of smartpin SYNC serial, please? I know I've seen a few posts with some code and pointers but I can't seem to any good examples of setting up the smartpins with SYNC serial RX. I know that using 3 smartpins to handle the bulk of SPI is possible, I'm just fighting trying to make it work. I've tried a number of different ways but I'm missing getting things synced. I was finally able to figure out how to use a pin as a free-running clock at least!


    Right now I've got this:
        sp_sync_rx  = %0000_0011_000_0000000000000_00_11101_0  '' +3
        sp_sync_cfg = %0_00111
    
    ..
    
            dirl    o
            wrpin   #sp_clk_cfg,o    'sync tx
            wxpin   #sp_sync_cfg ,o     '7 bits +1, pre
            dirh    o               'enable smartpin
            
            rep     @.end_rd, #8
                drvl    c
                drvh    c 
    .end_rd       
            rdpin   r,o
            dirl    o
    
    ..
    
    

    I'm about to attempt to use the smartpins to OUTPUT, since I can't quite figure out getting data in. At first I though I needed to invert Bpin… I'm idling the clock high and when enabling the pin with DIRH I believe it samples the pin on steady state, not on low to high transition. I'd really like to sample on the low to high transition so instead of inverting the Bpin, I think I need to adjust the enabling of the smartpin but I'm really not sure. I've been through the Smartpin section of the doc so many times i'm just not getting it. Some PASM would really help!


    *EDIT
    fixed typing error ozpropdev pointed out. Still no dice. I'm thinking I need a rdpin before the clock loop. More to explore later. The further I dig into the smartpins, the more questions I have!
  • evanhevanh Posts: 15,091
    I think everyone has bit-bashed it. The clock pin is a slight pain to understand.

    Async serial is another story, no clock pin and the data rate is often a lot slower so it's useful to let the hardware finish off the shifting while running other code.
  • @pilot0315 - agreed, I have no problems with that. Bear in mind that this thread is about Smart Pin docs and as such any "responses" are there for the general public and there will always be the odd post that is not quite on topic. You should realize though that since I wrote TAQOZ I would have to write the guts of it in assembler, so the source is always a very good place to go to if you want to see how it was done. More than one forumista has picked up Prop assembler this way. This is also where the interactivity of it comes into play, you see the simple SPI transmit routine and how it is written in PASM, and in TAQOZ you can interact with that module and even modify it with immediate feedback. However, I will leave it at that with just the code snippet from TAQOZ that bit bashes SPI.
    ' SPIWB ( byte -- )
    ' Shift 8 bits from data[0..7] out and leave data on stack (restored with other bytes zeroed)
    '
    SPIWR8		shl     tos , #24               ' left justify 8-bit data s
    		mov	r1,#8
    SPIWR		drvl	ss
    		drvl    sck
    		call	#POPX			' POP VALUE '
    SPITX8		rep     @.L1,r1
    		 rol     X,#1 wc               ' output next msb
            	 outc    mosi
                     outnot  sck                     ' clock
                     outnot  sck                     ' clock
    .L1            ret
    
  • @cheezus
    A quick look at your code snippet one thing stood out.
    rep     #.end_rd, #8
    
    I think should be
    rep     @.end_rd, #8
    

  • @cheezus
    You also need to shift the received data by 24 bits.
    Here's an example.
    'Smartpin loopback test of sync. Tx and Rx modes 
    'for P2-ES Eval board
    
    dat	org
    
    		hubset	#0
    
    		drvl	sck
    
    'setup smartpin for sync tx and supply inverted clock from tx + 1
    
    		wrpin	##%0000_1001_000_0000000000000_01_11100_0,tx
    		wxpin	#$20 + 7,tx
    		dirh	tx
    
    'setup smartpin for sync Rx and supply clock from rx + 2, data from rx + 1
    
    		wrpin	##%0001_0010_000_0000000000000_00_11101_0,rx
    		wxpin	#$0 + 7,rx
    		dirh	rx
    
    'send bytes on tx pin and receive bytes on rx pin
    
    		loc	ptra,#@msg
    .loop		rdbyte	pb,ptra++ wz
    	if_nz	wypin	pb,tx
    	if_nz	call	#txrx
    	if_nz	jmp	#.loop
    done		jmp	#$
    		
    txrx		rep	@.loop,#8	'send 8 clocks
    		outh	sck
    		waitx	#1
    		outl	sck
    		waitx	#1
    .loop		
    		rdpin	pa,rx
    		shr	pa,#24		'received byte
    
    		cmp	pa,pb wz	'both leds lit if match
    		drvl	#56		'alternate leds lit if mismatch
    		drvnz	#57
    		waitx	##25_000_000
    		drvh	#56
    		drvz	#57
    		waitx	##25_000_000
    		ret	wcz
    
    rx		long	1		'smartpin locations
    tx		long	2
    sck		long	3
    
    		orgh	$400
    
    msg		byte	"Smartpins",0
    
  • evanhevanh Posts: 15,091
    Hacked that for tighter timings. Loopback tested to 290 MHz sysclock fail point, same as the streamer tests. Probably requires further adjustment for a real SPI peripheral though.
    'Smartpin loopback test of sync. Tx and Rx modes 
    'for P2-ES Eval board
    
    dat	org
    
    		hubset	#0
    
    		wrpin	##1<<16, sck		'registered pin
    		drvl	sck
    
    'setup smartpin for sync tx and supply inverted clock from tx + 1
    
    		wrpin	##(%0000_0001<<24)+(1<<16)+%01_11100_0, tx	'clock from tx + 1, registered pin
    		wxpin	#$20 + 7,tx
    		dirh	tx
    
    'setup smartpin for sync Rx and supply clock from rx + 2, data from rx + 1
    
    		wrpin	##(%0001_1010<<24)+(1<<16)+%11101_0, rx		'inverted clock from rx + 2, data from rx + 1, registered pin
    		wxpin	#$0 + 7,rx
    		dirh	rx
    
    'send bytes on tx pin and receive bytes on rx pin
    
    		loc	ptra,#@msg
    .loop		rdbyte	pb,ptra++ wz
    	if_nz	wypin	pb,tx		'load shifter and place first bit on OUT
    	if_nz	call	#txrx
    	if_nz	jmp	#.loop
    done		jmp	#$
    		
    txrx		rep	@.loop,#8	'send 8 clocks, 4 sysclocks per SPI clock
    		outh	sck		'tx clock shift out next bit, takes sysclocks for tx to reach pin
    		outl	sck		'rx clock shift in existing bit before tx changes, takes more sysclocks for rx to see change
    .loop
    		waitx	#6		'twiddle thumbs while the lag from OUT to pin to smartpin propagates
    		rdpin	pa,rx
    		shr	pa,#24		'received byte
    
    		cmp	pa,pb wz	'both leds lit if match
    		drvl	#56		'alternate leds lit if mismatch
    		drvnz	#57
    		waitx	##25_000_000
    		drvh	#56
    		drvz	#57
    		waitx	##25_000_000
    		ret	wcz
    
    rx		long	1		'smartpin locations
    tx		long	2
    sck		long	3
    
    		orgh	$400
    
    msg		byte	"Smartpins",0
    
    
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