So what we need here is for some enterprising person to devise a service for chips along the lines of what OHSPARK does for PCBs. https://oshpark.com/
The OSHPARK idea is to collect a bunch of customer PCB designs, arrange them into one big board design, then get some PCB house to make that. Then chop the resulting board up into each customers little boards.
One could imagine collecting a bunch of customers silicon widget designs, in Verilog say, arranging them all onto a single chip for tape out. Then just bond out the different parts of the resulting chip for each customer.
All of a sudden that $35K is down to $3.5K per customer.
If all the design rules are pinned down and predictable, which they should be for these old technologies, this should be possible. If it works in FPGA it should work in raw silicon.
I tried talking to a bunch of chip design guys about this kind of thing over beer in Mountain View last summer. They looked at me like I was crazy...
Heater.,
I think you're on to something there. Great idea. It actually sounds feasible.. with only my gut for consultancy, of course. But I have a feeling something like that will be in our reasonably near future. It just feels right.
The OSHPARK idea is to collect a bunch of customer PCB designs, arrange them into one big board design, then get some PCB house to make that. Then chop the resulting board up into each customers little boards.
One could imagine collecting a bunch of customers silicon widget designs, in Verilog say, arranging them all onto a single chip for tape out. Then just bond out the different parts of the resulting chip for each customer.
All of a sudden that $35K is down to $3.5K per customer.
? - That does not quite stack up.
Chip Shuttles are already a thing, and OSHPARK run just like a shuttle, ie everyone's unique board is sliced off the larger FAB'd piece.
A single die, with multiple bonding, carries every unused item cost, and exposes everyones IP.
I can't see any commercial problem for which bigger, more expensive die is the answer. Hmm, maybe student projects (no expected production volumes) ?
Sounds like wholesale cost on a 180nm mask set is down to $35k now.
Very good to hear.
That, coupled with the high speed of small changes you report, means a Rev B fix for any (minor?) P2 issue, has less risk of killing P2 stone dead due to cost.
To be honest, now that I think about it, I remember where my "great idea" came from.
One of those chip designer guys I met in over beers in an Irish bar in Mountain View said as follows: If you really want to get your Verilog into silicon you can do it for free. All you have to do is get friendly with the guys in some university computer engineering department, convince them your plan is not totally stupid, and they can sneak your design into a shuttle run along with the usual student projects.
There we have it. The OSHPARK thing for silicon is already going on somehow. For the students in the hallowed labs of Berkley or wherever.
One day, one of those students will graduate into the real world and make that idea available.
As for gut consultancy. I was never into that idea much but I'm sure my brain is shrinking, I know my gut is growing. Which one is going to win?
cost of a 350nm mask set has dropped to $7,000 and the tape-out-to-delivery time is down to 6 weeks.
So assuming someone's prototypes (same process no flash) checked out OK, what do you think it would cost for a minimum production run of wafers nowadays? (a dozen wafers or whatever)
We had a meeting with some of their ESD engineers and they recommended that we make some modifications to our ESD structures. I was thinking, "Oh, no, this is going to take another day." Nathan had all those edits done in about 20 minutes. it took me a little longer just to modify my schematic.
As a sad side comment: you had a meeting with the good guys, the ones whose aiming is to help preserve things (ESD experts).
It would be great if you had a chance to arrange another meeting, now with their evil counterparts, that is, the guys whose expertise is focused into blowing things up (e-fuses)!
But, IIRC, the whole e-fuse thing was long gone and buried.
$7k for 350nm masks - wow. Thats kickstarter territory.
P1B with 64 i/o, anyone?
Or a P1 with more HUB RAM because one of the reasons for more I/O was adding external RAM. Even 60KB hub ram and 4KB Booter & Spin Interpreter would be a big improvement because it gives more diversity. The 16KB of Font ROM is rarely used, and even the SIN/LOG tables are not used much, so they are better to be RAM which can still be loaded with FONT/SIN/LOG as required.
There were some very minor changes done in the P1V that would also be worthwhile including.
QFP64 or QFP84 package would be ideal.
Would also be worthwhile spending the time asking about FLASH/EEPROM - IIRC the CAT24C512 is made on their (OnSemi) 350nm line.
So I wonder what a shuttle (total cost) for say 100 dies and how much to put that into a QFP would cost in total ???
BTW there are companies (besides shuttles)that put together different designs on a wafer, like OSHPark do for pcb designs. Just don't recall who they are ATM. Perhaps they are not passing on the design savings
Or a P1 with more HUB RAM because one of the reasons for more I/O was adding external RAM. Even 60KB hub ram and 4KB Booter & Spin Interpreter would be a big improvement because it gives more diversity. The 16KB of Font ROM is rarely used, and even the SIN/LOG tables are not used much, so they are better to be RAM which can still be loaded with FONT/SIN/LOG as required.
ROM is much smaller than SRAM, so you do not get a 1:1 trade off.
There were some very minor changes done in the P1V that would also be worthwhile including.
QFP64 or QFP84 package would be ideal.
Package is an interesting question, as present P1 die is quite large, and fills the package void.
I see QFP64 comes in many choices
TQFP64 : 14x14mm body 0.8mm pitch - same pitch as TQFP32
TQFP-64 : 12 x 12 mm body 0.65 mm pitch - same pitch as TQFP44
TQFP-64 : 10x10mm body 0.5 mm pitch - same body as TQFP44
TQFP64 : 7*7 mm body; 0.4 mm pitch
Note however that P1 is not a simple verilog-part, it includes full custom PLL/VCO/BOD/LFOSC/HFOSC portions
I wonder what clock speed a Verilog (auto-P&R) part would deliver at 350nm - could be somewhat less than 80MHz ?
cost of a 350nm mask set has dropped to $7,000 and the tape-out-to-delivery time is down to 6 weeks.
So assuming someone's prototypes (same process no flash) checked out OK, what do you think it would cost for a minimum production run of wafers nowadays? (a dozen wafers or whatever)
The 350nm wafers are 8 inch and under $1,000 each. A minimum order would be 20 wafers. You could fit over 3,000 dice of 3mm x 3mm on one of those wafers. So, for under $20k, you could get over 60k dice. There's packaging costs, too, and automated testing would cost something to develop.
Nathan the layout guy was telling me that they're using their C5 process (500nm) to build interposers for stacked dice. This means just two metal layers and no active layers. This could, say, mate a Prop2 die to an 8-pin 32Mb flash die, so that P62 and P63 pins could be internal to the package and afford some code protection. he said the cost on something like that is only $0.06.
We had a meeting with some of their ESD engineers and they recommended that we make some modifications to our ESD structures. I was thinking, "Oh, no, this is going to take another day." Nathan had all those edits done in about 20 minutes. it took me a little longer just to modify my schematic.
As a sad side comment: you had a meeting with the good guys, the ones whose aiming is to help preserve things (ESD experts).
It would be great if you had a chance to arrange another meeting, now with their evil counterparts, that is, the guys whose expertise is focused into blowing things up (e-fuses)!
But, IIRC, the whole e-fuse thing was long gone and buried.
Henrique
Before giving up on the e-fuses, I did get to understand that there is a 0.25% fail-to-blow rate. That would necessitate some kind of redundancy which may still prove insufficient in the field. That was just more than I wanted to sign up for.
I've been at OnSemi in Pocatello, Idaho this week. These guys are extremely fast and smart. Their layout guy, Nathan, punched our layout into shape in a couple of hours. He's like a shark. We had a meeting with some of their ESD engineers and they recommended that we make some modifications to our ESD structures. I was thinking, "Oh, no, this is going to take another day." Nathan had all those edits done in about 20 minutes. it took me a little longer just to modify my schematic.
Everything is coming together very quickly, so that what is left is mainly place-and-route. That is underway, already, and I will post some pictures today.
The place-and-route engineer mentioned something that blew me away yesterday. Across from the office building where these guys work is their 350nm fab. He mentioned that the cost of a 350nm mask set has dropped to $7,000 and the tape-out-to-delivery time is down to 6 weeks. The mask set for the 350nm Propeller 1 chip was $60,000 and it took 12 weeks to get parts back. This means that very small companies can design chips now. The barrier to entry is extremely low these days. It is mainly a matter of knowledge.
$60,000 10-12 years ago would also be closer to $100k in today's money!!
So $7k is a huge reduction.
This could, say, mate a Prop2 die to an 8-pin 32Mb flash die, so that P62 and P63 pins could be internal to the package and afford some code protection. he said the cost on something like that is only $0.06.
Dumb question- Would flash manufacturers happily and reliably sell bare dies? (this is the kind of info you can't find in a book)
Edit- It looks like you can buy die parts at digikey. (Not significantly cheaper though)
The hint to use an interposer layer, serving as an interface to stack an EEPROM is super. Sincere thanks to Nathan, for making it.
I know that this is unlikely to doesn't has happened yet, but, have you ever considered creating two extra digital-only (3.3 V) buried pins, with relaxed ESD and drive-capability (fan-out) concerns, since they will be only connected to the stacked EEPROM?
It would be great if they could be segregated to be accessed only by COG 0, just after reset, wich, in turn, would mask them out and regain access to the externaly, generaly-available ones, using parts of the logic you've already created, to control the now defunct e-fuses programming-and-checking proccess.
Since the small die to be stacked, being a known to be good part, does already has such structures (ESD and drive capability) designed into it, thus preserving itself, and don't letting any hazardous voltages to propagate from its own connections, to affect the die laying under it.
I know at this stage, space availability tends to become critical, if not yet totaly compromised with all that logic and memory instances, already placed at the die, but it would be great if it can make, someway.
Looking for any area to spare, perhaps the internal rom area could be reduced to a tiny-winny minimum, and the EEPROM increased in turn, if needed.
...
I know that this is unlikely to doesn't has happened yet, but, have you ever considered creating two extra digital-only (3.3 V) buried pins, with relaxed ESD and drive-capability (fan-out) concerns, since they will be only connected to the stacked EEPROM?...
This stacked die idea has come up before, and one fundamental problem is all addressable pins are already used in the 64 io of P2.
Seems easy to raise money, even if some of the claims are somewhat hyped.
In what way are the claims of SiFive hyped?
As a bunch of really smart engineers pursuing a worthwhile goal I can't think of anyone more deserving of the money.
Contrast, for example, the billions invested in Facebook, Uber and others.
The Western Digital thing is already old news. Nvidia is also planning to use RISC V in their future graphics cards.
Seems big players are keen to avoid paying royalties,...
Yes, but I think it's bigger than just saving money on royalties. It's about independence, flexibility and self-determination.
...but their silicon is not openly available.
Let's be clear. RISC V is only an open specification of a processor instruction set architecture. License free and patent unencumbered. It does not say anything about how you implement that ISA or how open your implementation is.
Think of it like this: The C language is an open standard. But if you write a C compiler you can keep it as closed or open as you like. Think GCC and LLVM vs MS Visual whatever.
and the Eval Board price, rather brings home the lead ARM has on the Merchant-MPU business, when you compare a RaspPi price...
Yes, the Linux running SiFive Freedom dev board is crazy expensive at about a thousand dollars.
However the HiFive dev board is only $59. Not bad.
And the chips are only $5 each if you want some to play with.
Clearly ARM has a big lead in the Merchant-MPU business. But those silicon Merchant's could turn around in no time.
Intel could dabble in this too, with some benefit. Anything that is not-ARM ?
Interestingly, Intel has an ARM license still. They could do ARM if they wanted to. They even did make ARM devices some years ago. They sold that business out some time ago. I forget who to.
I bet Intel could make a blinding RISC V machine.
Strangely enough, it was a miserable wet day today, so I started work on my own RISC V implementation in SpinalHDL...
Let's see : ...highly disruptive RISC-V technologies to the marketplace.
Hmm, it's yet-another 32/64b register based MPU design, built on the same standard FAB lines other MPUs use ...
" SiFive will continue to provide innovative solutions that will fundamentally change the semiconductor industry."
Hmm, a few sample devices, at higher prices than ARMs, are quite a long way short of "fundamentally change" - still, it is worth tracking real silicon.
"RISC-V delivers a platform for innovation unshackled from the proprietary interface of the past. "
No idea what he thought he was trying to say, but the interfaces like Ethernet and DDR4, are set by the industry - the core has nothing to do with the interfaces ?
And the chips are only $5 each if you want some to play with.
Let's look at that FE310-G000 part :
• 8kB OTP Program Memory
• 8kB Mask ROM
• 16kB Instruction Cache
• 16kB Data SRAM
• 6x6mm 48-lead QFN package ( 0.4mm pad pitch )
• 3 Independent PWM Controllers
• External RESET pin
• JTAG, SPI and UART interfaces.
• QSPI Flash interface.
• Requires 1.8V and 3.3V supplies
The QSPI is interesting, but 8kB OTP is quite small/ancient and the claimed 320MHz rather fights with the QSPI memory, limiting it to code that can run on-chip.
(not clear if you can lock parts of the cache?)
Does that FE310-G000 look like a part with a 20 year design life ? Nope, still experimental.
I would say that with the likes of Western Digital and Nvidia using RISC V in their future designs, that is disruptive.
Quite likely the next 10 gazillion IoT devices could be RISC V based. That is disruptive if you happen to be ARM and hoping to get royalties from that market.
...yet-another 32/64b register based MPU design, built on the same standard FAB lines other MPUs use ...
To be clear, again, RISC V is only an Instruction Set Architecture (ISA) specification. It says nothing about implementation or FAB lines.
Yes, one could say it is "Yet another". But if you want to build a processor today you will need compilers and tools to support it. That means ARM, MIPS, possibly SPARK. Which are all license encumbered. Heck, why not RISC V, where all that is available with no chains.
Hmm, a few sample devices, at higher prices than ARMs, are quite a long way short of "fundamentally change" - still, it is worth tracking real silicon.
Yes, higher prices than ARMs. Give them a break, they only just got started producing tasters of the idea. It's like saying Parallax Propellers are expensive. Of course they are.
No idea what he thought he was trying to say, but the interfaces like Ethernet and DDR4, are set by the industry - the core has nothing to do with the interfaces ?
The phrase was "unshackled from the proprietary interface of the past"
The "interface" in question being the most fundamental thing in computers. The interface between software and the hardware that runs it is the Instruction Set Architecture.
Let's look at that FE310-G000 part :
Yes. I'm sure that chip does not stand up against many other examples.
But again, that is missing the point. RISC V is only an instruction set architecture. It's not a chip. Or a FAB process.
I look at it like this: Let's say I have some millions of dollars to spend. And I have a great idea for a new chip gadget. Why would I waste half a year or more negotiating for an ARM licence and then paying royalties when I could just use RISC V and get on with it? With the help of SiFive or some others.
Let's see how it all pans out.
Oh, I could rephrase your last sentence as:
"Does that Intel 8088 look like a part with a 20 year design life ? Nope, still experimental."
The phrase was "unshackled from the proprietary interface of the past"
The "interface" in question being the most fundamental thing in computers. The interface between software and the hardware that runs it is the Instruction Set Architecture.
That makes even less sense, as anyone using a Compiler does not really care anymore about Instruction Set Architecture.
They just want their code to run.
...anyone using a Compiler does not really care anymore about Instruction Set Architecture.
They just want their code to run.
That is very true.
But let's look at things from the other end of the telescope. Rather than looking down as a software designer to the instruction set, let's look up as a hardware builder to the instruction set.
If I want to build a new hardware gizmo, quite likely I need a processor in there. That means I need to implement an instruction set. It would be a huge advantage for me to implement an instruction set for which there already was a compiler, a debugger, an OS like Linux and all the other tools available. I can't spend time and money on all that.
I could use the ARM ISA and leverage all that software, but oops, that takes months of negotiation and then I have to pay royalties.
x86 is out of the question.
Similarly with other options.
But, hey, I can use RISC V. Free of charge, no strings attached, all tools available already. Why not?
Now, from this end of the telescope we start to see why Nvidia and Western Digital are into the idea. I'm very sure there are many other such developments we have not heard of yet.
If I want to build a new hardware gizmo, quite likely I need a processor in there. That means I need to implement an instruction set...
No, it does not mean that - you can also simply choose an existing processor that fits the bill. That's how most start-ups work these days.
Those 'royalities' are hidden in the price of the part.
Useful MCU prices continue to fall rapidly - you can buy a useful 8 bit MCU for sub 30c, and I see a useful 32bit ARM is now sub 40c/3k
"Engineering is the art of making what you need, from what you can get"
Gads, I am such an old timer. I quit at the 286, 8085 and the BS2.
I have so much to learn...
Until 2006/2007 was just a tiny step further, being stuck at the Scenix SX line, since 2000, till I've found Parallax and the Propeller.
And it took me another six year (2012), before I could find time to dwelve into its belly.
My fingers calculator still insists doing maths in tens of nanosecond steps. Most of the time, I have to divide by thousand, mentally, only to stay tunned at P2' pace.
...We have a lot to learn everyday. Even if I forget more than I learn each day
I saw my old high-school chemistry teacher at my parents' church over the weekend. He's in his 80's now. I told him how I remember so many things he taught, like molality vs. molarity, and redox equations. He said, "You probably know more than me, these days."
RaspPi skipped all of that imagined problem, by simply choosing a chip that existed already, and designed with that.
Wait a minute. The original Raspi concept of Eben Upton did not use an ARM. His prototypes were ATMEGA based. Eben happened to land a job at Broadcom, who happened to have an old ARM SoC that they would let him use on the cheap for his "hobby" project.
Every Raspi is still including an ARM royalty.
Why do you say it's an "imagined" problem? If you want to build your own processor today it's real enough. Buy the ARM design, or other, or pay for software development to support you own custom instruction set.
Parallax has this problem with the C compilers and IDE's for the Propeller.
No, it does not mean that - you can also simply choose an existing processor that fits the bill. That's how most start-ups work these days.
Those 'royalities' are hidden in the price of the part.
That is true. If you are buying processor or more likely SoC parts today.
I'm talking about people building chips. Building their own silicon. They can license an ARM or whatever Instruction Set Architecture. Which will take months of negotiating and then royalty payments. Or they can just throw a RISC V ISA machine in there for free. And have all the tool support they need.
I'm talking about people building chips. Building their own silicon.
That is a very small club, and the very high mask costs at the bleeding edge, are a much bigger problem than royalties. MIPS charge less than ARM, and are still active in the custom space.
Of course, what those guys do, matters little to the Embedded design space that those in this forum inhabit.
A very successful P2 may mean Parallax can look at a Risc-V + P2 in the future ?
But with Nvidia and Western Digital and no doubt others in there it's getting bigger.
Certainly high mask costs are a problem for everyone. The likes of SiFive are hoping to help with that. Going from millions of dollars to get a test chip in your hands to hundreds of thousands.
A Propeller with a RISC V core would be great. Can't wait!
Comments
https://oshpark.com/
The OSHPARK idea is to collect a bunch of customer PCB designs, arrange them into one big board design, then get some PCB house to make that. Then chop the resulting board up into each customers little boards.
One could imagine collecting a bunch of customers silicon widget designs, in Verilog say, arranging them all onto a single chip for tape out. Then just bond out the different parts of the resulting chip for each customer.
All of a sudden that $35K is down to $3.5K per customer.
If all the design rules are pinned down and predictable, which they should be for these old technologies, this should be possible. If it works in FPGA it should work in raw silicon.
I tried talking to a bunch of chip design guys about this kind of thing over beer in Mountain View last summer. They looked at me like I was crazy...
I think you're on to something there. Great idea. It actually sounds feasible.. with only my gut for consultancy, of course. But I have a feeling something like that will be in our reasonably near future. It just feels right.
? - That does not quite stack up.
Chip Shuttles are already a thing, and OSHPARK run just like a shuttle, ie everyone's unique board is sliced off the larger FAB'd piece.
A single die, with multiple bonding, carries every unused item cost, and exposes everyones IP.
I can't see any commercial problem for which bigger, more expensive die is the answer. Hmm, maybe student projects (no expected production volumes) ?
Very good to hear.
That, coupled with the high speed of small changes you report, means a Rev B fix for any (minor?) P2 issue, has less risk of killing P2 stone dead due to cost.
One of those chip designer guys I met in over beers in an Irish bar in Mountain View said as follows: If you really want to get your Verilog into silicon you can do it for free. All you have to do is get friendly with the guys in some university computer engineering department, convince them your plan is not totally stupid, and they can sneak your design into a shuttle run along with the usual student projects.
There we have it. The OSHPARK thing for silicon is already going on somehow. For the students in the hallowed labs of Berkley or wherever.
One day, one of those students will graduate into the real world and make that idea available.
As for gut consultancy. I was never into that idea much but I'm sure my brain is shrinking, I know my gut is growing. Which one is going to win?
So assuming someone's prototypes (same process no flash) checked out OK, what do you think it would cost for a minimum production run of wafers nowadays? (a dozen wafers or whatever)
As a sad side comment: you had a meeting with the good guys, the ones whose aiming is to help preserve things (ESD experts).
It would be great if you had a chance to arrange another meeting, now with their evil counterparts, that is, the guys whose expertise is focused into blowing things up (e-fuses)!
But, IIRC, the whole e-fuse thing was long gone and buried.
Henrique
Or a P1 with more HUB RAM because one of the reasons for more I/O was adding external RAM. Even 60KB hub ram and 4KB Booter & Spin Interpreter would be a big improvement because it gives more diversity. The 16KB of Font ROM is rarely used, and even the SIN/LOG tables are not used much, so they are better to be RAM which can still be loaded with FONT/SIN/LOG as required.
There were some very minor changes done in the P1V that would also be worthwhile including.
QFP64 or QFP84 package would be ideal.
Would also be worthwhile spending the time asking about FLASH/EEPROM - IIRC the CAT24C512 is made on their (OnSemi) 350nm line.
So I wonder what a shuttle (total cost) for say 100 dies and how much to put that into a QFP would cost in total ???
BTW there are companies (besides shuttles)that put together different designs on a wafer, like OSHPark do for pcb designs. Just don't recall who they are ATM. Perhaps they are not passing on the design savings
Q: What do you think would fit in the same die size as the P2 on 180nm ???
A: Probably a P1B/P1B with 512KB Hub RAM, at least 16 Cogs with 4KB and perhaps 32 Cogs, 64 I/O (standard OnSemi digital only)
ROM is much smaller than SRAM, so you do not get a 1:1 trade off.
Package is an interesting question, as present P1 die is quite large, and fills the package void.
I see QFP64 comes in many choices
TQFP64 : 14x14mm body 0.8mm pitch - same pitch as TQFP32
TQFP-64 : 12 x 12 mm body 0.65 mm pitch - same pitch as TQFP44
TQFP-64 : 10x10mm body 0.5 mm pitch - same body as TQFP44
TQFP64 : 7*7 mm body; 0.4 mm pitch
Note however that P1 is not a simple verilog-part, it includes full custom PLL/VCO/BOD/LFOSC/HFOSC portions
I wonder what clock speed a Verilog (auto-P&R) part would deliver at 350nm - could be somewhat less than 80MHz ?
The 350nm wafers are 8 inch and under $1,000 each. A minimum order would be 20 wafers. You could fit over 3,000 dice of 3mm x 3mm on one of those wafers. So, for under $20k, you could get over 60k dice. There's packaging costs, too, and automated testing would cost something to develop.
Nathan the layout guy was telling me that they're using their C5 process (500nm) to build interposers for stacked dice. This means just two metal layers and no active layers. This could, say, mate a Prop2 die to an 8-pin 32Mb flash die, so that P62 and P63 pins could be internal to the package and afford some code protection. he said the cost on something like that is only $0.06.
Before giving up on the e-fuses, I did get to understand that there is a 0.25% fail-to-blow rate. That would necessitate some kind of redundancy which may still prove insufficient in the field. That was just more than I wanted to sign up for.
$60,000 10-12 years ago would also be closer to $100k in today's money!!
So $7k is a huge reduction.
Dumb question- Would flash manufacturers happily and reliably sell bare dies? (this is the kind of info you can't find in a book)
Edit- It looks like you can buy die parts at digikey. (Not significantly cheaper though)
I know that this is unlikely to doesn't has happened yet, but, have you ever considered creating two extra digital-only (3.3 V) buried pins, with relaxed ESD and drive-capability (fan-out) concerns, since they will be only connected to the stacked EEPROM?
It would be great if they could be segregated to be accessed only by COG 0, just after reset, wich, in turn, would mask them out and regain access to the externaly, generaly-available ones, using parts of the logic you've already created, to control the now defunct e-fuses programming-and-checking proccess.
Since the small die to be stacked, being a known to be good part, does already has such structures (ESD and drive capability) designed into it, thus preserving itself, and don't letting any hazardous voltages to propagate from its own connections, to affect the die laying under it.
I know at this stage, space availability tends to become critical, if not yet totaly compromised with all that logic and memory instances, already placed at the die, but it would be great if it can make, someway.
Looking for any area to spare, perhaps the internal rom area could be reduced to a tiny-winny minimum, and the EEPROM increased in turn, if needed.
This stacked die idea has come up before, and one fundamental problem is all addressable pins are already used in the 64 io of P2.
https://www10.edacafe.com/nbc/articles/1/1576473/SiFive-Secures-$50.6-Million-Funding-Advance-RISC-V-Based-Semiconductors
Seems easy to raise money, even if some of the claims are somewhat hyped.
This number was interesting :
Western Digital, which has pledged to produce 1 billion RISC-V cores.
Seems big players are keen to avoid paying royalties, but their silicon is not openly available.
and the Eval Board price, rather brings home the lead ARM has on the Merchant-MPU business, when you compare a RaspPi price...
Intel could dabble in this too, with some benefit. Anything that is not-ARM ?
Thanks for the heads up on that news snippet. In what way are the claims of SiFive hyped?
As a bunch of really smart engineers pursuing a worthwhile goal I can't think of anyone more deserving of the money.
Contrast, for example, the billions invested in Facebook, Uber and others.
The Western Digital thing is already old news. Nvidia is also planning to use RISC V in their future graphics cards. Yes, but I think it's bigger than just saving money on royalties. It's about independence, flexibility and self-determination. Let's be clear. RISC V is only an open specification of a processor instruction set architecture. License free and patent unencumbered. It does not say anything about how you implement that ISA or how open your implementation is.
Think of it like this: The C language is an open standard. But if you write a C compiler you can keep it as closed or open as you like. Think GCC and LLVM vs MS Visual whatever. Yes, the Linux running SiFive Freedom dev board is crazy expensive at about a thousand dollars.
However the HiFive dev board is only $59. Not bad.
And the chips are only $5 each if you want some to play with.
Clearly ARM has a big lead in the Merchant-MPU business. But those silicon Merchant's could turn around in no time. Interestingly, Intel has an ARM license still. They could do ARM if they wanted to. They even did make ARM devices some years ago. They sold that business out some time ago. I forget who to.
I bet Intel could make a blinding RISC V machine.
Strangely enough, it was a miserable wet day today, so I started work on my own RISC V implementation in SpinalHDL...
Let's see :
...highly disruptive RISC-V technologies to the marketplace.
Hmm, it's yet-another 32/64b register based MPU design, built on the same standard FAB lines other MPUs use ...
" SiFive will continue to provide innovative solutions that will fundamentally change the semiconductor industry."
Hmm, a few sample devices, at higher prices than ARMs, are quite a long way short of "fundamentally change" - still, it is worth tracking real silicon.
"RISC-V delivers a platform for innovation unshackled from the proprietary interface of the past. "
No idea what he thought he was trying to say, but the interfaces like Ethernet and DDR4, are set by the industry - the core has nothing to do with the interfaces ?
Let's look at that FE310-G000 part :
• 8kB OTP Program Memory
• 8kB Mask ROM
• 16kB Instruction Cache
• 16kB Data SRAM
• 6x6mm 48-lead QFN package ( 0.4mm pad pitch )
• 3 Independent PWM Controllers
• External RESET pin
• JTAG, SPI and UART interfaces.
• QSPI Flash interface.
• Requires 1.8V and 3.3V supplies
The QSPI is interesting, but 8kB OTP is quite small/ancient and the claimed 320MHz rather fights with the QSPI memory, limiting it to code that can run on-chip.
(not clear if you can lock parts of the cache?)
Does that FE310-G000 look like a part with a 20 year design life ? Nope, still experimental.
I would say that with the likes of Western Digital and Nvidia using RISC V in their future designs, that is disruptive.
Quite likely the next 10 gazillion IoT devices could be RISC V based. That is disruptive if you happen to be ARM and hoping to get royalties from that market. To be clear, again, RISC V is only an Instruction Set Architecture (ISA) specification. It says nothing about implementation or FAB lines.
Yes, one could say it is "Yet another". But if you want to build a processor today you will need compilers and tools to support it. That means ARM, MIPS, possibly SPARK. Which are all license encumbered. Heck, why not RISC V, where all that is available with no chains. Yes, higher prices than ARMs. Give them a break, they only just got started producing tasters of the idea. It's like saying Parallax Propellers are expensive. Of course they are. The phrase was "unshackled from the proprietary interface of the past"
The "interface" in question being the most fundamental thing in computers. The interface between software and the hardware that runs it is the Instruction Set Architecture. Yes. I'm sure that chip does not stand up against many other examples.
But again, that is missing the point. RISC V is only an instruction set architecture. It's not a chip. Or a FAB process.
I look at it like this: Let's say I have some millions of dollars to spend. And I have a great idea for a new chip gadget. Why would I waste half a year or more negotiating for an ARM licence and then paying royalties when I could just use RISC V and get on with it? With the help of SiFive or some others.
Let's see how it all pans out.
Oh, I could rephrase your last sentence as:
"Does that Intel 8088 look like a part with a 20 year design life ? Nope, still experimental."
It's amazing what can happen...
That makes even less sense, as anyone using a Compiler does not really care anymore about Instruction Set Architecture.
They just want their code to run.
Exactly my point, it has yet to pan out...
I have so much to learn...
But let's look at things from the other end of the telescope. Rather than looking down as a software designer to the instruction set, let's look up as a hardware builder to the instruction set.
If I want to build a new hardware gizmo, quite likely I need a processor in there. That means I need to implement an instruction set. It would be a huge advantage for me to implement an instruction set for which there already was a compiler, a debugger, an OS like Linux and all the other tools available. I can't spend time and money on all that.
I could use the ARM ISA and leverage all that software, but oops, that takes months of negotiation and then I have to pay royalties.
x86 is out of the question.
Similarly with other options.
But, hey, I can use RISC V. Free of charge, no strings attached, all tools available already. Why not?
Now, from this end of the telescope we start to see why Nvidia and Western Digital are into the idea. I'm very sure there are many other such developments we have not heard of yet.
Shame you quit then. The general PC world did not get interesting till the 32 bit i386.
But, I'm sure you had better things to be doing.
We have a lot to learn everyday. Even if I forget more than I learn each day
RaspPi skipped all of that imagined problem, by simply choosing a chip that existed already, and designed with that.
No, it does not mean that - you can also simply choose an existing processor that fits the bill. That's how most start-ups work these days.
Those 'royalities' are hidden in the price of the part.
Useful MCU prices continue to fall rapidly - you can buy a useful 8 bit MCU for sub 30c, and I see a useful 32bit ARM is now sub 40c/3k
"Engineering is the art of making what you need, from what you can get"
Until 2006/2007 was just a tiny step further, being stuck at the Scenix SX line, since 2000, till I've found Parallax and the Propeller.
And it took me another six year (2012), before I could find time to dwelve into its belly.
My fingers calculator still insists doing maths in tens of nanosecond steps. Most of the time, I have to divide by thousand, mentally, only to stay tunned at P2' pace.
You're no way alone!
I saw my old high-school chemistry teacher at my parents' church over the weekend. He's in his 80's now. I told him how I remember so many things he taught, like molality vs. molarity, and redox equations. He said, "You probably know more than me, these days."
Every Raspi is still including an ARM royalty.
Why do you say it's an "imagined" problem? If you want to build your own processor today it's real enough. Buy the ARM design, or other, or pay for software development to support you own custom instruction set.
Parallax has this problem with the C compilers and IDE's for the Propeller. That is true. If you are buying processor or more likely SoC parts today.
I'm talking about people building chips. Building their own silicon. They can license an ARM or whatever Instruction Set Architecture. Which will take months of negotiating and then royalty payments. Or they can just throw a RISC V ISA machine in there for free. And have all the tool support they need.
That is a very small club, and the very high mask costs at the bleeding edge, are a much bigger problem than royalties. MIPS charge less than ARM, and are still active in the custom space.
Of course, what those guys do, matters little to the Embedded design space that those in this forum inhabit.
A very successful P2 may mean Parallax can look at a Risc-V + P2 in the future ?
But with Nvidia and Western Digital and no doubt others in there it's getting bigger.
Certainly high mask costs are a problem for everyone. The likes of SiFive are hoping to help with that. Going from millions of dollars to get a test chip in your hands to hundreds of thousands.
A Propeller with a RISC V core would be great. Can't wait!