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Long time no see... — Parallax Forums

Long time no see...

m00tykinsm00tykins Posts: 73
in Propeller 2
Hey all,

I'm back after a couple years, just with a quick suggestion: Could Parallax please make a dedicated (non-forum) webpage kept up-to-date with P2 progress? I'm sure there are lots of people like me who have "left" the forums but still check the parallax website once every few months to see if it's done yet. I'm not trying to rush anything, but would appreciate more transparency on the status of it. Nothing fancy, and it doesn't even need to display an ETA either. Just what stage it's currently at.

Thanks!

Comments

  • jmgjmg Posts: 15,173
    Try this :
    http://forums.parallax.com/categories/propeller-2-multicore-microcontroller
    and scan the items there, just the names alone gives you some idea
  • Peter JakackiPeter Jakacki Posts: 10,193
    The P2 label is a bit of misnomer as I have seen the chip evolve past P3, P4, then P5, and now with this new SKIP instruction it is different again :) Even those who are trying to keep up can't keep up. Only when it is finally locked into silicon will we stand a chance. In which I guess the Parallax home page will make it plainly obvious that "P2" is available for designing in. That's when I will regain my interest.
  • m00tykinsm00tykins Posts: 73
    jmg wrote: »
    Try this :
    http://forums.parallax.com/categories/propeller-2-multicore-microcontroller
    and scan the items there, just the names alone gives you some idea

    The forum thread names give no useful information. And I meant for those people who are tired of deciphering random forum threads for more information, as I've been doing for the last few years but have grown tired of.
  • m00tykinsm00tykins Posts: 73
    Peter Jakacki wrote: »
    The P2 label is a bit of misnomer as I have seen the chip evolve past P3, P4, then P5, and now with this new SKIP instruction it is different again :) Even those who are trying to keep up can't keep up. Only when it is finally locked into silicon will we stand a chance. In which I guess the Parallax home page will make it plainly obvious that "P2" is available for designing in. That's when I will regain my interest.

    What are you talking about Peter? I've never heard of this, though I wouldn't be surprised if I've missed something. Hence my request for more transparency, for those of us who are not fortunate enough to have the time for browsing the parallax forums daily/weekly.
  • Peter JakackiPeter Jakacki Posts: 10,193
    The original P2 was supposed to be a P1 with more memory and more I/O, but it didn't stop there so it effectively IMO became a P3, then there was P4 which was called "P2 HOT" for very good reason which led to a rethink so being conservative that would make it a P5 but it continues to evolve in FPGA form. But you shouldn't worry too much, it will be very good when it is actually available although it will bear very little resemblance to the P1 and there will be a much steeper learning curve if you want to delve in under the hood.
  • jmgjmg Posts: 15,173
    m00tykins wrote: »
    jmg wrote: »
    Try this :
    http://forums.parallax.com/categories/propeller-2-multicore-microcontroller
    and scan the items there, just the names alone gives you some idea

    The forum thread names give no useful information. And I meant for those people who are tired of deciphering random forum threads for more information, as I've been doing for the last few years but have grown tired of.

    I guess that depends on how you define useful and just what you expected ?

    Let's try some examples

    USB Testing 12...11 12
    - 12 pages around USB testng on P2, or did you already know all about P2 USB abilities, or have no interest in USB ?

    New Spin 12...30 31/i]
    - 32 pages of New Spin started Feb 18, shows P2-Spin work is underway.

    Random/LFSR on P2 12...13 14
    13 pages, Started march 1st, covers Random number generator work

    and of course
    Prop2 FPGA files!!! - Updated 28 February 2017 - Version 16a

    Lots of info in that heading alone, lastest FPGA update was done on Feb 28 and is now at v16
  • KeithEKeithE Posts: 957
    I think that he just wants a simple page where he can check on the status every quarter or so. If you want the status in a nutshell - the microarchitecture specification for P2 is not yet frozen. If you check back in a quarter then hopefully it will be frozen, and you can try to find out the status of the RTL testing.
  • xanaduxanadu Posts: 3,347
    You could probably email Parallax support and get a shorter more official answer.
  • potatoheadpotatohead Posts: 10,261
    edited 2017-03-23 19:15
    We are currently testing and making final changes to instruction set. This is being done in the context of the SPIN interpreter and various testing code being written on FPGA board.

    This is close to done. We have flirted with an instruction lock.

    My gut says a month or so remains at this stage.

    Steps remaining:

    Booter crypto, other startup basics ROM
    Final Layout review
    Synthesis
    Depending on that outcome, a round of tweaks.
    prep for shuttle
    Shuttle run
    Test test chips
    Move to production ready, likely get a production run done for broader development (boards, tools, docs)
    At some point, move to general release.

    In parallel with that:
    Get spin and PASM core tools done
    Docs
    Demo educators boards
    Integrate Blockly
    Gcc, OpenSPIN, IDE general use tools
    Various Demos, sample code, etc...

    That is my take, based on discussion here.




  • Cluso99Cluso99 Posts: 18,069
    Add to that...
    Ask OnSemi about costs/issues in adding on-chip OTP/FLASH/EEPROM.
  • jmgjmg Posts: 15,173
    potatohead wrote: »
    Shuttle run
    Test test chips
    Move to production ready, likely get a production run done for broader development (boards, tools, docs)
    At some point, move to general release.
    that's the optimists version, the realists version goes like :

    Shuttle run
    Probe Test wafers, if appear alive, package.
    Test test chips
    Generate Errata Sheet
    Decide, based on Errata, if this mask can go into production, or needs a respin ?
    Also decide based on Errata, if full production release is done, or a second shuttle of engineering samples to allow 'early access designers' PCB development with errata list, whilst fixes are applied in a 3rd shuttle run...
    When errata is small enough, then move to production ready
  • MByronMByron Posts: 26
    KeithE wrote: »
    I think that he just wants a simple page where he can check on the status every quarter or so. If you want the status in a nutshell - the microarchitecture specification for P2 is not yet frozen. If you check back in a quarter then hopefully it will be frozen, and you can try to find out the status of the RTL testing.

    I also would like a way to see in a few lines the progress and when to expect hardware. I have 11 Prop P1 boards and am a strong fan of the Prop with hopes to see a P2 in my future. A dedicated "ballpark" status access would be great.
    I need to feel in the loop!
  • TubularTubular Posts: 4,702
    Here's what I think might help, and be relatively easy to maintain...

    1. Elevate the "Prop2 FPGA Files!!!" to be a sticky at the top of the stack
    2. Update the forum descriptive header (photo below) to include what's being worked on now (Spin2 + supporting instructions), as well as what the next step is going to be
    3. At end of forum description, say to click on first post in top thread for latest information.

    In my opinion the google doc is answer, because its kept up to date, has a good opening description, plus solid detail to show this has moved well beyond 'planning'.

    p2forum.png
    p2forum.png
    970 x 457 - 67K
  • Cluso99Cluso99 Posts: 18,069
    Not wanting to sound negative, but, sad to say.....

    For anyone interested in seeing a progress report for the purpose of using a P2, they are wasting their time.

    The P2 will be done if/when its done.

    No expectations of any dates can be made - this has been proven.
  • Peter JakackiPeter Jakacki Posts: 10,193
    Cluso99 wrote: »
    Not wanting to sound negative, but, sad to say.....

    For anyone interested in seeing a progress report for the purpose of using a P2, they are wasting their time.

    The P2 will be done if/when its done.

    No expectations of any dates can be made - this has been proven.

    But it has always been proven over the years that there is plenty of optimism that "it's just about done" which is true for the FPGA implementation, silicon though is a different story. How I would love and crave those analog functions that only real silicon can deliver.

  • potatoheadpotatohead Posts: 10,261
    jmg wrote: »
    potatohead wrote: »
    Shuttle run
    Test test chips
    Move to production ready, likely get a production run done for broader development (boards, tools, docs)
    At some point, move to general release.
    that's the optimists version, the realists version goes like :

    Shuttle run
    Probe Test wafers, if appear alive, package.
    Test test chips
    Generate Errata Sheet
    Decide, based on Errata, if this mask can go into production, or needs a respin ?
    Also decide based on Errata, if full production release is done, or a second shuttle of engineering samples to allow 'early access designers' PCB development with errata list, whilst fixes are applied in a 3rd shuttle run...
    When errata is small enough, then move to production ready

    Entirely likely. But, I'll stay with the optimism.

    Peter, me too.

  • Brian FairchildBrian Fairchild Posts: 549
    potatohead wrote: »
    My gut says a month or so remains at this stage.

    Steps remaining:

    <<<SNIP>>>

    In parallel with that:

    <<<SNIP>>>

    How does one person (Chip) work in parallel with himself?

    Production quality documentation alone will take 6 man-months.
  • potatoheadpotatohead Posts: 10,261
    edited 2017-03-24 15:43
    Production docs could be generated right now regarding a ton of the chip functionality. I suspect some of those efforts to happen the moment a synthesis gets committed. As an example.
  • Peter JakackiPeter Jakacki Posts: 10,193
    potatohead wrote: »
    Production docs could be generated right now regarding a ton of the chip functionality. I suspect some of those efforts to happen the moment a synthesis gets committed. As an example.

    You certainly are optimistic but ultimately unrealistic as those "production docs" will have to be generated by someone in the know when they know what they don't know now, otherwise they could be wasting their time, and a lot of time has already been wasted on documenting what was and now isn't. It can't be Chip at this stage but once chips are available I'm sure we all could contribute to some real testing and "production docs". Assuming of course that nothing goes wrong with the first prototypes.....


  • potatoheadpotatohead Posts: 10,261
    The bulk of the instructions won't change. 80 percent of the chip can be documented from what Chip has put out there and FPGA validation.

    Yes, it's a risk. And worst case, shuttle needs a repeat. I would still wager 80 percent can be documented.

  • jmgjmg Posts: 15,173
    Brian Fairchild wrote: »
    Production quality documentation alone will take 6 man-months.

    I'm not sure what "Production quality documentation" actually means here ?

    There is already a 376 line spreadsheet of P2 opcodes, and a 57 Page "Parallax Propeller 2 Documentation" published.
    The next useful steps around P2 DOCs, would be software examples.

    I'd be more worried about "Production Quality Tools", which will take more than 6 man-months.

    A Simulator is looking more important by the day, but that's not even been discussed yet...




  • Dave HeinDave Hein Posts: 6,347
    I think a production quality document would be something like the 399-page Propeller Manual for the P1. However, the P2 will probably require 1000 pages to cover the same level of detail. Hopefully, Chip will get lots of support from Parallax and the developer community to write the documentation and production quality tools.

    Spinsim supports many of the P2 instructions, but it hasn't been updated for a while. Once the P2 design is frozen I'll update it to match the latest version of the FPGA.
  • jmgjmg Posts: 15,173
    Dave Hein wrote: »
    Spinsim supports many of the P2 instructions, but it hasn't been updated for a while. Once the P2 design is frozen I'll update it to match the latest version of the FPGA.

    Sounds good - will that simulate the smart pins, or just the opcodes & memory space ?
  • Dave HeinDave Hein Posts: 6,347
    I haven't implemented any of the smart pins logic, so it currently supports only opcodes and memory. I hope to add some of the smart pins functionality later on.
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