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Ozpropdev or Cluso99, what's that PNut assembler addressing problem, again??? — Parallax Forums

Ozpropdev or Cluso99, what's that PNut assembler addressing problem, again???

cgraceycgracey Posts: 14,152
edited 2017-02-25 07:29 in Propeller 2
I can't find it and I can't recreate it. I though it had to do with 9-bit relative jumps being extended with ##, but those seem to assemble okay. It was something else, and you pointed it out 5 times, but I can't remember. Just shows I should have fixed it when it came up. Sorry. Any help appreciated.

Comments

  • cgraceycgracey Posts: 14,152
    I think it has to do with backward-branching ##S instructions. I'm seeing some ugly behavior.
  • cgraceycgracey Posts: 14,152
    No, actually, it looks correct.

    I'll keep looking for those posts.
  • ozpropdevozpropdev Posts: 2,792
    Chip
    I think this is the issue your thinking of.
    {
CCCC 1011001 CZI DDDDDDDDD SSSSSSSSS        CALLD   D,S/#rel9   {WC,WZ}
}
dat	org

	calld	myret,##hub	' <-- Error - Expected a constant,unary operator or "("
	drvh	#34
here	jmp	#here

oz2	drvh	#33
	jmp	myret

myret	long	0

	orgh	$400
hub	drvh	#32
	jmp	myret
  • cgraceycgracey Posts: 14,152
    Thanks, Ozpropdev!

    I just played around with your example. There is a rule in the assembler that relative S jumps can't cross between cog/LUT and hub. Your example declares "hub" under an ORGH, making the assembler think it's hub-exec code, even though there is some practical address overlap in the current assembler. This is going to take some thinking to figure out how to handle.

    I'll get v16 out and worry about this afterwards.
  • cgraceycgracey Posts: 14,152
    Ozpropdev, would you mind testing all the FPGA images again for v16? It took all day to get them ready and I minded all the details, but I haven't tested them - only the -A9 version. No obligation here. It would just save me some time. I'll put a link here, shortly, if you're up to it.
  • Cluso99Cluso99 Posts: 18,069
    I have been out. As you now know, it wasn't me who found the problem.
  • ozpropdevozpropdev Posts: 2,792
    cgracey wrote: »
    Ozpropdev, would you mind testing all the FPGA images again for v16? It took all day to get them ready and I minded all the details, but I haven't tested them - only the -A9 version. No obligation here. It would just save me some time. I'll put a link here, shortly, if you're up to it.
    No worries Chip.
    FPGA's warmed up and ready to go! :)

  • cgraceycgracey Posts: 14,152
    ozpropdev wrote: »
    cgracey wrote: »
    Ozpropdev, would you mind testing all the FPGA images again for v16? It took all day to get them ready and I minded all the details, but I haven't tested them - only the -A9 version. No obligation here. It would just save me some time. I'll put a link here, shortly, if you're up to it.
    No worries Chip.
    FPGA's warmed up and ready to go! :)

    Super! Here it is:

    https://drive.google.com/file/d/0B9NbgkdrupkHb3VSWHB1b2xOdjg/view?usp=sharing
  • cgraceycgracey Posts: 14,152
    I'll start getting the rest of the update ready, then. Thanks a lot for testing those.
  • ozpropdevozpropdev Posts: 2,792
    edited 2017-02-25 08:46
    Thanks Chip!
    I'll get to it!
  • cgraceycgracey Posts: 14,152
    ozpropdev wrote: »
    Thanks Chip!
    I'll get to it!

    Any problems, so far?
  • cgraceycgracey Posts: 14,152
    Ozpropdev, if all goes well, could you please make a post on the "PROP2 FPGA FILES!!!" thread announcing the new update at the top of the thread? I don't know how much longer I'll be up, but I'll wait to hear from you for a little while. Thanks.
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