General Planning
Ramon
Posts: 484
Original Title Edited. Was : 'General Planning - First IC samples 2017 (Q4)'
The purpose of this thread was to check the grade of completeness of P2 development, and the grade of commitment for completion. It was an attempt to obtain any more detailed information than just "the P2 will be done when it is ready."
P2 is still in alpha stage, even if the instruction set is frozen. Frozen doesn't mean completed, and doesn't mean it cannot change.
Ken said that there is no schedule planned, and that any schedule or plan depends on Chip. And Chip just says what is the next step he would do and that is. You all can check bellow the responses from Ken and Chip.
(Space reserved for official Planning.)
This is the planning if there is no official plan:
1) Test instruction set (1 month, end of 1st Quarter).
Start compiler and documentation.
2) Final release v17 (Fix bugs).
Send verilog to treehouse (begining of April)
3) Shuttle (2Q)
4) Get first shuttle ICs and send to package vendor (3Q).
5) Deliver first ICs before end of year (end of 3Q/begining of 4Q).
The purpose of this thread was to check the grade of completeness of P2 development, and the grade of commitment for completion. It was an attempt to obtain any more detailed information than just "the P2 will be done when it is ready."
P2 is still in alpha stage, even if the instruction set is frozen. Frozen doesn't mean completed, and doesn't mean it cannot change.
Ken said that there is no schedule planned, and that any schedule or plan depends on Chip. And Chip just says what is the next step he would do and that is. You all can check bellow the responses from Ken and Chip.
(Space reserved for official Planning.)
This is the planning if there is no official plan:
1) Test instruction set (1 month, end of 1st Quarter).
Start compiler and documentation.
2) Final release v17 (Fix bugs).
Send verilog to treehouse (begining of April)
3) Shuttle (2Q)
4) Get first shuttle ICs and send to package vendor (3Q).
5) Deliver first ICs before end of year (end of 3Q/begining of 4Q).
Comments
We did not expect this date to come.
Chip, congratulations and thank you.
Enjoy the great work. Ease the pressure.
No more any questions asking when it will be done.
No more any reply saying "when it is ready".
Verilog is finished.
It is time now to define deadlines.
We need them.
We didn't liked deadlines not to put pressure on Chip.
He's now relieved. He has done his job. Verilog is finished.
It is time for Testers. ONE MONTH.
It is your turn, Chip will fix the bugs you found.
One month should be enough.
You have been testing since September 2015.
After that, Treehouse will start IC layout.
They must deliver GDSII in 3 months at most.
Yes, they can do that.
They have been working with parallax for how many months? 3 years?
Given that, I expect them to finish in 6 weeks.
Shuttle run around July or August.
First ICs will be sent to Parallax and IC packaging vendor.
First packaged samples around October.
First samples will be sent to those KEY TESTERS.
I personally vote for Ozpropdev to be delivered sample #1 for his outstanding contribution testing every single FPGA image for ALL FGPA boards since the first version.
Now you have a good reason to do a good job and impress the boss.
Remember that you have 1 month.
Yes, can be done.
We expected the firt samples at the end of 2016.
And we want the f***** IC this year 2017!
I will be watching for this plan to be executed without any delay.
P2 Calendar:
March Mo Tu We Th Fr Sa Su 24 25 26 27 28 29 30 31 April May June Mo Tu We Th Fr Sa Su Mo Tu We Th Fr Sa Su Mo Tu We Th Fr Sa Su 1 2 1 2 3 4 5 6 7 1 2 3 4 3 4 5 6 7 8 9 8 9 10 11 12 13 14 5 6 7 8 9 10 11 10 11 12 13 14 15 16 15 16 17 18 19 20 21 12 13 14 15 16 17 18 17 18 19 20 21 22 23 22 23 24 25 26 27 28 19 20 21 22 23 24 25 24 25 26 27 28 29 30 29 30 31 26 27 28 29 30 July August September Mo Tu We Th Fr Sa Su Mo Tu We Th Fr Sa Su Mo Tu We Th Fr Sa Su 1 2 1 2 3 4 5 6 1 2 3 3 4 5 6 7 8 9 7 8 9 10 11 12 13 4 5 6 7 8 9 10 10 11 12 13 14 15 16 14 15 16 17 18 19 20 11 12 13 14 15 16 17 17 18 19 20 21 22 23 21 22 23 24 25 26 27 18 19 20 21 22 23 24 24 25 26 27 28 29 30 28 29 30 31 25 26 27 28 29 30 31 October November December Mo Tu We Th Fr Sa Su Mo Tu We Th Fr Sa Su Mo Tu We Th Fr Sa Su 1 1 2 3 4 5 1 2 3 2 3 4 5 6 7 8 6 7 8 9 10 11 12 4 5 6 7 8 9 10 9 10 11 12 13 14 15 13 14 15 16 17 18 19 11 12 13 14 15 16 17 16 17 18 19 20 21 22 20 21 22 23 24 25 26 18 19 20 21 22 23 24 23 24 25 26 27 28 29 27 28 29 30 25 26 27 28 29 30 31 30 31Nice illusion, but nothing more.
Testing coverage will take more than 1 month, and you miss entirely Silicon Testing and Errata generation, which will be many weeks, and then comes the hard decision of to release with errata, or is a re-spin needed.
Shuttle parts are called Alpha / Engineering Samples for a reason
Even if 'release with errata' is decided, 'first chips' need a FAB production schedule in, and automated testers/self testing needs to be nailed down...
"A deadline is, simply put, optimism in its most Smile-kicking form."
>Test instruction set (1 month, end of 1st Quarter).
If someone really wants to help pro bono, then make a detailed plan. As far as I can tell there isn't a verification plan in place. How do you coordinate people without one? How do you know you're done without one? How does anyone even estimate test coverage of the RTL without having the RTL source available and a simulation environment setup?
I have no idea how the chips are tested in production. Perhaps Parallax is doing some DFT work with Treehouse and will have test logic (logic BIST/memory BIST) in place. Otherwise developing a test program and determining test coverage is hard and takes time and that's missing from the schedule. If you're using functional programs for test, then typically you would need to run them in simulation and perform fault grading. Then iterate when you find that your coverage is too low.
GCC took years on P1.
So did the IDE software.
OpenSpin took ages.
BlocklyProp has been going I think for 2 years. While now released and used, it's classed as Beta.
P2HOT had a number of dedicated testers. Many of those have moved on.
Apart from the basic instructions, not much has been tested.
IMHO, even now the P2 is "frozen", we are not going to see P2 any time soon
Can you point out which instructions have not been tested yet.
Hmmm.... That's a depressing thought. I'm sure Chip's x86 version of Spin2 will be done in time.
&
Tachyon for P2 should be very quick, as I understand that's largely working, and that has an advantage of a large test suite code base.
I wonder how quickly a PropBASIC for p2 can happen ?
Seems to not output binaries, but generates .spin file with Assembler, or LMM code choices ?
At a quick glance things like WAITCNT and WAITPNE etc will need code-generator changes, but much of the add/mov/jmp should be broadly portable ?
We don't need for RTL source, and we don't want chip to release the code to us.
He will release the RTL to Treehouse after 1 MONTH, when we finish to check the Instruction Set.
The instruction set IS our source.
The simulation enviroment setup is (are) the FPGA board(s) itself.
The FPGA is the DUT.
As you already know Parallax P2 is a single man project. Don't even try to force Chip to use the 'formal' verification plan as big companies (Intel, AMD, ARM, ...) as used to. They have different tools and resources.
A lot of people (Ozpropdev, Seairth, ...) have done this kind of testing before.
And they have found many bugs.
There is ONE MONTH to do 'Instruction Set' testing. Yes, It can be done.
They have been doing this kind of testing for this P2 'branch' since FPGA v1 (September 2015, 18 months ago).
I want to remind you that Treehouse has been working on P2 since at least 2 YEARS (January 2015). But could be maybe 3 years, as I cannot do a search for the old forum post (when Chip announced their collaboration).
What does 'released' mean? The date when the RTL is delivered to Treehouse?
I haven't read any post from Chip or Ken saying that. In fact I remember that Chip has said that there is no need to wait for SPIN to be finished in order to start with silicon manufacturing.
Not to be snarky, however what portion of the plan are you going to be responsible for?
Seems like a fair bit of 'unit' type testing has been done on different bits and pieces, however again, there needs to be a plan to insure rigorous, all-encompassing testing. Are there potential race conditions, etc, etc.
Do we even have a hard count of available, committed testers, and how do we insure that they are testing at the appropriate skill level?
We appear to be in goal range of final design.
However soon we want P2's, testing will take the time that it takes considering available resources.
It would really suck if the process were rushed, only to find something were missed which would require a respin.
We actually do operate under deadlines in Parallax, more than ever in the past ten years. At the moment we have 11 Professional Development courses planned across the country. Aside from training teachers, these courses provide a the goal where we force ourselves to achieve certain tasks: test and document the ActivityBot libraries and C blocks; test/document the WX blocks, produce the teacher's guide and about 150 other on-line pages of material. We have a systematically maintained internal planning tool. Where necessary, we drop requirements and rearrange efforts but the course delivery deadline can't change. There are no surprises in our planning along the way; it's a constant process of communication. If we don't deliver then we don't train teachers and we don't have new business in Fall 2017. That simple.
It's an example of a do-or-die situation, with everybody accepting the challenge. Parallax is ready to start winning again and we're going to do this quite well with the Blockly system and our educational documentation.
P2 certainly warrants a complete task-oriented timeline. We need it to place costs and obtain the various funding for the next $500K minimum needed to have chips in our inventory. Until the steps are taken to put this product in a Gannt chart everything is speculation, including the costs I estimated above, delivery dates, tool requirements, etc.
I've been here before, with P1 and our team (they're all still at Parallax). To really help this project move forward Chip needs to come to the office and meet with us to define the final steps. I generally know them (Spin Interpreter, manual layout revisions, synthesis of Verilog, test chip, test the test chip, production chip, test fixture firmware for packaging factory, datasheet, software, etc.). Defining these steps, the P2 can be put on a schedule.
I'm happy to help given a match of commitment and promise for completion, as moving my attention away from sales and professional development courses for teachers will have other negative effects on the business. Switching horses is a serious step for Parallax as it creates a span where part of Parallax goes dormant while we prepare for P2 - and revenue-generating activities must be ready to occur on a known timeline.
Chip would need to define the steps and dependencies, and then everything starts lining up.
Ken Gracey
P.S. Thinking out loud - to get serious about this we need to NOT repeat certain things we've done before. NO custom fonts in ROM or in Propeller Tool, OpenSpin must be finished before we have chips, etc. The choice of applications we choose to demonstrate must be carefully envisioned and delivered upon to match a target market. I don't know the current thinking of these parts, and I am better at asking questions at this stage than providing answers.
What is your plan? Do you also think it could be possible to have the first IC samples before then end of this year?
Do you plan to wait for SPIN (or any other HLL) for testing the P2 Instruction Set?
Will you Port P1 Spin into P2, ... make it 100% binary compatible, ... and test all OBEX code and applications?
I don't think that you need Spin, or any other HLL, to test P2 FPGA v16 Instruction Set.
Actually I think that after you finish SPIN for P2, you will have two unresolved problems :
- Test the P2 Instruction Set,
- and Test SPIN Interpreter.
I don't think that is needed or desirable.
There is only 1 MONTH to test the P2 FPGA v16 Instruction Set.
That is needed before you can send the RTL to Treehouse next month.
So they can route the IC layout, and deliver GDSII at 2Q,
then you can reserve shuttle for 3Q,
and have the first packaged IC samples around 4Q.
Are we on the same wavelength? Do you want the first IC samples before the end of this year?
With all due respect, I think you're being rather presumptuous in deigning to impose or even to suggest deadlines to Parallax. Let it go. The P2 will happen when it happens.
-Phil
Mike, creativity work is already done. Verilog is finished.
Now we have a rutinary job to execute. We need deadlines:
- Test instruction set (1 MONTH - 1 day) - Deliver bug-fixed RTL to Treehouse (March 24th) - Get GDSII from Treehouse (2Q) and joint it with outer ring (PADS) GDSII - Start Onsemi shuttle at (earlier 3Q), - Get first die ICs (end of 3Q) - keep some of them for parallax internal testing - send the rest to packaging vendor - Get first IC samples at 4Q 2017re: OpenSpin, you have my axe.
Sounds good, as far as it goes.
How do you check that nothing broke, in the smart pin modes, in the meantime ?
Where exactly did this magical and arbitrary 1 MONTH come from ??
Are you the majority shareholder in Parallax ?
Engineering Samples and Device Errata first ?
Phil, It was not my purpose to impose any date. I am very sorry If you or anyone else feel like that. I just want to point out that schedules might be needed again, now that verilog is finished (actually 'frozen').
Maybe I didn't chose the right word. Is it 'schedule' better that 'deadline'? (does 'deadline' have a negative meaning?). You will remember that deadlines were defined some years ago by Parallax themselves, but those were never meet. For (at least) two reasons we certainly know : the first, that P2 verilog was a creativity job (as Mike pointed out before); and second one, that 'Open-forum-design-style' invites for delays ('What if' ... , 'Chip, can you add' ...).
It was Parallax who decided that they wanted an open development. I don't mind if this thread is closed or erased, If they feel that deadlines should be keep secret (for any purpose) . At the end, the question I want to rise is only : is there any plan/schedule?. I just don't want to hear 'verilog is finished' or 'verilog is frozen'. I want to hear 'verilog is frozen/finished and now we plan to do this ...'. "The journey of a thousand miles begins with one step." Again if for some reason it should be keep secret, I am ok with that decission.
I pretty much feel the same, I don't want any rush. But if there is not any defined plan, will the P2 be ever finished?
The jobs do get done in the end. Workshop staff are a third of what they were and yet the managers want even everything working top notch even more. Sometimes we hire extra contractors. Sometimes the production staff just have to work around a broken part. Sometime just some tape does the job for the short term.
Right now, I'm just trying to get v16 out and it's enough to think about. Then, I want to concentrate on Spin 2. That's all I got.
Having a draft of SPIN 2 is gonna help too. We get an overlap in testing SPIN 2, in-line PASM, etc... It's a two-fer.