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P2 verification plan — Parallax Forums

P2 verification plan

VonSzarvasVonSzarvas Posts: 3,450
in Propeller 2
This discussion was created from comments split from: A "P2" - now or never - I'm off to join the ARMy.

Comments

  • KeithEKeithE Posts: 957
    Where is the P2 verification plan that people reference during testing?
  • jmgjmg Posts: 15,173
    VonSzarvas wrote: »
    This discussion was created from comments split from: A "P2" - now or never - I'm off to join the ARMy.

    Hmm, I see that other thread has been closed.
    Does that mean you will be manually generating sub-threads for all the valid points that were raised ?
  • VonSzarvasVonSzarvas Posts: 3,450
    No. But feel free to start threads with new questions.
  • KeithEKeithE Posts: 957
    Also I was wondering if there are instruction set exercisers for the prop1 and prop2 opcodes? I found this thread, but maybe there's a later thread:

    http://forums.parallax.com/discussion/154461/is-there-a-testbench-for-opcodes-instruction-set-exersizer

    I would assume that something like this is run after every FPGA build. Nice to know for both people working on P1 FPGAs and P2.
  • jmgjmg Posts: 15,173
    KeithE wrote: »
    Also I was wondering if there are instruction set exercisers for the prop1 and prop2 opcodes? ...

    I'm guessing Chip runs some test passes before all FPGA releases, but getting full coverage instruction set exercisers that would catch all bugs, is a monumental task.

    The active working projects may be better at catching system-related bugs ?
    (eg I think the USB test code, is now r14 valid at least ?)+

    It certainly should be possible to do a simpler subset that confirms every opcode at least does what was expected.

    There should also be similar 'echo' self test suites around Smart Pins. I've not seen much done on that ?

    eg Config a Smart pin to each mode and read-back using another smart pin, to confirm 'as expected'

    These can form user tutorials, in the release product.




  • cgraceycgracey Posts: 14,152
    For the Prop2 Hot, I had a series of opcode tests I'd run after each revision. It was all table-driven and efficient to work with. I need to get that going again. These days, I just run all the demos and make sure they work, which is not a very complete test.
  • evanhevanh Posts: 15,915
    KeithE wrote: »
    Also I was wondering if there are instruction set exercisers for the prop1 and prop2 opcodes?
    Testing has been happening. Oz, and Cluso too I think, had run groups of testing back when there was lots of instruction additions. Oz is always experimenting and found many odd combinations that Chip has fixed, many of which were PNut issues. GarryJ's USB code just looks amazing.

    The interrupt on REP bug that Oz found was a good find. Although it only mattered for the debug IRQ I think.
  • KeithEKeithE Posts: 957
    Chip - if you have any links to your old p2 hot approach that would be interesting to see.
  • cgraceycgracey Posts: 14,152
    edited 2017-02-21 22:17
    Here is some P2-Hot test code. Note that it uses indirect register addressing, which was really convenient:
    ''**********
''*  TEST  *
''**********
'
' INCMOD/DECMOD
' MOVS/MOVD/MOVI
'

DAT

' tester code - changes byte[entry] to $00 when done, returns $00 (pass) or $01 (fail) at byte[entry+1]

entry			org

			cogid	cntinit			'init cnt to get going

' run tests

			setinda	#r

			mov	inda,incmod0		'incmod test
			incmod	inda++,incmod1	wz,wc
			mov	inda,#0
			pushzc	inda++

			mov	inda,incmod2
			incmod	inda++,incmod3	wz,wc
			mov	inda,#0
			pushzc	inda++

			mov	inda,incmod4
			incmod	inda++,incmod5	wz,wc
			mov	inda,#0
			pushzc	inda++

			mov	inda,incmod6
			incmod	inda++,incmod7	wz,wc
			mov	inda,#0
			pushzc	inda++


			mov	inda,decmod0		'decmod test
			decmod	inda++,decmod1	wz,wc
			mov	inda,#0
			pushzc	inda++

			mov	inda,decmod2
			decmod	inda++,decmod3	wz,wc
			mov	inda,#0
			pushzc	inda++

			mov	inda,decmod4
			decmod	inda++,decmod5	wz,wc
			mov	inda,#0
			pushzc	inda++

			mov	inda,decmod6
			decmod	inda++,decmod7	wz,wc
			mov	inda,#0
			pushzc	inda++


			mov	inda,movs0		'movs test
			movs	inda++,movs1	wz,wc
			mov	inda,#0
			pushzc	inda++

			mov	inda,movs2
			movs	inda++,movs3	wz,wc
			mov	inda,#0
			pushzc	inda++


			mov	inda,movd0		'movd test
			movd	inda++,movd1	wz,wc
			mov	inda,#0
			pushzc	inda++

			mov	inda,movd2
			movd	inda++,movd3	wz,wc
			mov	inda,#0
			pushzc	inda++


			mov	inda,movi0		'movi test
			movi	inda++,movi1	wz,wc
			mov	inda,#0
			pushzc	inda++

			mov	inda,movi2
			movi	inda++,movi3	wz,wc
			mov	inda,#0
			pushzc	inda++





' verify test results

			setinds	#a,#r

			mov	x,#$1C
verify			cmp	inda++,indb++	wz
	if_z		djnz	x,#verify

	if_z		wrword	passval,ptrb[0]		'write result ($0000=pass, $0100=fail)
	if_nz		wrword	failval,ptrb[0]


pass			notp	#0
	if_z		jmp	#pass

fail			getlfsr	0		nr, wc
			setpc	#0
			jmp	#fail


' questionable results (default = 0)

r			long	0[$80]


' correct answers

a			long	$00000000,%11					'$00 incmod test
			long	$00000004,%00
			long	$00000001,%00
			long	$00000000,%11

			long	$00000002,%00					'$08 decmod test
			long	$00000004,%01
			long	$00000000,%10
			long	$00000010,%01

			long	$12345755,%00					'$10 movs test
			long	$00000000,%10

			long	$1236AA78,%00					'$14 movd test
			long	$00000000,%10

			long	$AAB45678,%00					'$18 movi test
			long	$00000000,%10

			long	-1						'$1C

' predefined

cntinit			long	$400

incmod0			long	$00000003
incmod1			long	$00000003

incmod2			long	$00000003
incmod3			long	$00000004

incmod4			long	$00000000
incmod5			long	$7FFFFFFF

incmod6			long	$00000000
incmod7			long	$00000000


decmod0			long	$00000003
decmod1			long	$00000001

decmod2			long	$00000000
decmod3			long	$00000004

decmod4			long	$00000001
decmod5			long	$7FFFFFFF

decmod6			long	$00000000
decmod7			long	$00000010


movs0			long	$12345678
movs1			long	$FFFFFF55

movs2			long	$000001FF
movs3			long	$F0000E00


movd0			long	$12345678
movd1			long	$FFFFFF55

movd2			long	$0003FE00
movd3			long	$F00C0E00


movi0			long	$12345678
movi1			long	$FFFFFF55

movi2			long	$FF800000
movi3			long	$F0000E00


passval			long	$0000
failval			long	$0100



' reserved

x			res	1
y			res	1
  • jmgjmg Posts: 15,173
    As part of verification, how does P2 stack up alongside IEC-60730

    Broadly, this means (amongst other things) items like separate watchdog oscillators, and ability to check an OSC is present, before enabling it as SysCLK source. Some include missing-clock detectors that reset.

    P2 has two RC osc, so I think it gets close ?

    Other vendors offer libraries that do some self verification at run time:
    one example:
    http://www.silabs.com/products/development-tools/software/efm8-iec-60730-library
  • KeithEKeithE Posts: 957
    Thanks for posting that Chip.

    For anyone who doesn't know what I mean by verification plan, here's an old book about it:

    https://archive.org/details/springer_10.1007-978-1-4615-0473-3

    I know that Parallax doesn't want to operate quite this way, so maybe just skip to Appendix D on page 207 for a quick overview.
  • potatoheadpotatohead Posts: 10,261
    A while back someone, I think it was jerryg, made a test harness. Ospropdev has one too.

    Updating this, sharing it among the rest of us would help a lot. I had part of one I used to test things, but it's many revisions back.

    Personally, I haven't done much with Smart Pins yet.

    I did do a fair bit with the streamer, and Rayman's recent mouse pointer helped validate some "on the fly" change cases. There are more of those to do. They worked prior to buffering the streamer, but glitched when instruction execute didn't match end of stream. Fixed. :D

    Also, a while back, I tried S-video, didn't see color and luma properly separated. Now that there are some docs, it's probably a good idea to test all the output cases.

    Maybe we could list what we've tested?
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