P1V in the Pipistrello version compiles fine for the ECP5 target. The report shows something like 97 MHz max if I remember correct. I have not done any detailed timing analysis.
I just wait for my FleaOhm board to test if the P1V really works and how fast.
Heater
I meant they will not charge for the tools as long as competitors give their for free. All providers have built in restrictions in the free versions.
Therefore they are basically software vendors. Which makes all these software licensing terms and restrictions understandable. That is all they have!
No, they have total control over production and sales of the FPGA chips, even if they are using contract manufacturing lines to do it. If the IceStorm tools were the only way to program all FPGAs, these companies would still be selling the chips.
But, without the lock-ins of their own tools, they would be competing more as a commodity though.
Given that the FPGA vendors "secret source" is only software. Then anyone can do it. Given enough resources.
Currently there is a desire to provide reprogrammable logic as a service in the cloud. By the likes of Google, Amazon and Microsoft.
How long can it be before those guys realize the best way to do this is to collaborate on an "open FPGA system" that they can all use. Cut out the middleman.
As as happened with the Linux kernel.
IceStorm/Yosys and other projects show that this is possible.
P1V in the Pipistrello version compiles fine for the ECP5 target. The report shows something like 97 MHz max if I remember correct. I have not done any detailed timing analysis.
I just wait for my FleaOhm board to test if the P1V really works and how fast.
Thanks Ariba, sounds promising.
I do still hold out hope that the ECP5 FPGA will be usable in the end and that its clock distribution skew becomes manageable so hold timing analysis succeeds. I recall that the ECP5 has slightly more limited PLL capabilities compared to Altera FPGAs and the P1V's clock generator block were causing some of the drama with the P1V hold timing problems I was getting when I was trying to derive and distribute both 160MHz and 80MHz clocks from some common 480MHz PLL frequency.
I didn't have much luck with that stuff yet unfortunately but another P1V codebase may see different outcomes. I may possibly have started with a different variant of code to you (can't recall exactly as it been too long now). Might have been something from Jac's github repo instead of the original release from Chip, however I think that code has also been changing since.
Investment in Linux required a monopoly moving up through the ranks to galvanise the desire to collaborate.
To whom are you referring to when you say "monopoly" there?
I don't recall any particular major corporate power ever being "the" prime mover for Linux.
Rather, what I have seen over the decades is that many such organizations have pitched in and collaborated on the Linux eco-system. Intel, IBM, Google, Facebook, Amazon and a host of others. Now even Microsoft, whose boss famously derided Linux and Open Source software as a "cancer".
Linux didn't grow from enthusiasm alone
True. Practical necessity is the major reason why Linux and all the Free and Open Source software around has grown so well over the years.
IIRC the Altera Stratix 10 FPGA's were fabricated by Intel using Intel's tri-gate technology.
Re: Linux (Unix), It's interesting that Microsoft was such a big player in the late 70's,early 80's with it's Xenix licensing.
IIRC they licensed it to lot of companies such as Intel, IBM and even Apple.
Investment in Linux required a monopoly moving up through the ranks to galvanise the desire to collaborate.
To whom are you referring to when you say "monopoly" there?
I don't recall any particular major corporate power ever being "the" prime mover for Linux.
Cripes, it was a defensive collaboration! WinTel being the monopolistic threat. The PC started right at the bottom of the food chain, chewing up everything in it's path as the billions rolled in for Intel and M$.
Ok, now I get what you mean. The "duopolistic" threat.
I guess I'm a bit of an outsider. Windows, or even MS-DOS was never really a thing in my life. Except for a brief period in 1998 or so. I had spent years working on all kind of other systems. The PC and such was regarded as a toy.
The PC got serious with the arrival of the 386 in 1985. But there was not generally available 32 bit operating system till 15 years later! Linux, started in 1991 was not an attack on any duoploy, it just arrived to fill a big hole.
Meanwhile I had been working with embedded systems in various companies for many years. I noticed that often they had a hard time because some operating system or language their products depended on no longer existed. Good for me, as they hired me to help fix that mess. So at one company, when I found they were digging yet another proprietary hole for themselves, I suggested they forget thinking about the traditional embedded operating system vendors and use Linux instead. They thought I was nuts. Took a while to turn them around.
Little did I know that embedded systems builders around the world had the same idea!
P1V in the Pipistrello version compiles fine for the ECP5 target. The report shows something like 97 MHz max if I remember correct. I have not done any detailed timing analysis.
I just wait for my FleaOhm board to test if the P1V really works and how fast.
Thanks Ariba, sounds promising.
I do still hold out hope that the ECP5 FPGA will be usable in the end and that its clock distribution skew becomes manageable so hold timing analysis succeeds. I recall that the ECP5 has slightly more limited PLL capabilities compared to Altera FPGAs and the P1V's clock generator block were causing some of the drama with the P1V hold timing problems I was getting when I was trying to derive and distribute both 160MHz and 80MHz clocks from some common 480MHz PLL frequency.
I didn't have much luck with that stuff yet unfortunately but another P1V codebase may see different outcomes. I may possibly have started with a different variant of code to you (can't recall exactly as it been too long now). Might have been something from Jac's github repo instead of the original release from Chip, however I think that code has also been changing since.
I've looked at the Diamond project again. It was 94.8 MHz max and the worst path was in the ALU, so the CPU should work with that frequency. This was a 4 cog version for the 12kLUT ECP5.
I have not used the original Verilog for clock generation. I simplified it in that I used a clock input from a pin as the cpu_clock and generate a x 2 clock with a PLL for pll_clk.
I think we don't need all the configuration options of the real Propeller in a P1V, you always can modify the Verilog source for special clock settings.
Ok that sounds like an interesting approach Andy and I agree not all the various clock options are required. A lot of the problems I had were directly related to the P1V clocking block so if you got rid of a lot of it that may well have helped.
One thing I noticed on the FleaFPGA Ohm board in particular is that Valentin uses a 25MHz xtal frequency, not the more common 50MHz other boards often use. That also has some impact on how the 160/80MHz can be generated - perhaps 800/10 and 800/5 are possible if the PLL multiplier and divider ranges can reach those numbers. Personally I would really like a core PLL clock of 480MHz as it lets you get 96MHz for USB use too. Though that may be still achievable in other ways if you cascade PLLs, in theory anyway.
The ECP5 used on that board has 2 PLLs. Valentin used 25MHz for getting 750MHz then divides down to 75MHz and 375MHz for the HDMI graphics clocks needed for HDTV resolutions. My thought was to also get a 50MHz clock from that first PLL (divide by 15) and feed it into the second PLL for P1V use.
I've looked at the Diamond project again. It was 94.8 MHz max and the worst path was in the ALU, so the CPU should work with that frequency. This was a 4 cog version for the 12kLUT ECP5.
I have not used the original Verilog for clock generation. I simplified it in that I used a clock input from a pin as the cpu_clock and generate a x 2 clock with a PLL for pll_clk.
I think we don't need all the configuration options of the real Propeller in a P1V, you always can modify the Verilog source for special clock settings.
Andy
Thats pretty exciting, Andy. Is that with a -6, -7, or -8 speed grade?
It was a -6 speedgrade, I never remember what is fast and what is slow....
BTW I looked at the warnings and the only warnings I see are the one that identifiers are used before declared - should be easy to fix.
4 Cogs use 67% of a ECP5-12, maybe 6 cogs will fit, but I need some free logic for extensions.
The ECP5-25 of the FleaOhm should easy allow 8 cogs plus extensions.
Comments
P1V in the Pipistrello version compiles fine for the ECP5 target. The report shows something like 97 MHz max if I remember correct. I have not done any detailed timing analysis.
I just wait for my FleaOhm board to test if the P1V really works and how fast.
Heater
I meant they will not charge for the tools as long as competitors give their for free. All providers have built in restrictions in the free versions.
As far as I understand none of the FPGA vendors actually own their own chip FABs and actually make their own devices.
Therefore they are basically software vendors. Which makes all these software licensing terms and restrictions understandable. That is all they have!
So, what the world needs is an Open Source FPGA that can be made by TSMC or whoever.
Things like IceStorm show that this is possible.
But, without the lock-ins of their own tools, they would be competing more as a commodity though.
Lattice makes no really big FPGAs.
Given that the FPGA vendors "secret source" is only software. Then anyone can do it. Given enough resources.
Currently there is a desire to provide reprogrammable logic as a service in the cloud. By the likes of Google, Amazon and Microsoft.
How long can it be before those guys realize the best way to do this is to collaborate on an "open FPGA system" that they can all use. Cut out the middleman.
As as happened with the Linux kernel.
IceStorm/Yosys and other projects show that this is possible.
But that commodity spectre will be scary for them. They are unlikely to voluntarily collaborate while the status quo holds.
As counter examples to your argument I offer the following:
1) The Linux kernel.
Which is now supported by the likes of Google, IBM, Amazon, Microsoft etc.
2) The Clang/LLVM compiler. Which is now supported by the likes of Google, Apple, IBM, Amazon, Microsoft etc.
3) Countless other open source efforts supported by big business.
I see no reason why the FPGA world should not succumb to this.
And like Apple, even that wouldn't have survived if the Internet wasn't already in place. As a result, the free Web became the new battle ground.
Now, arguably, the Web is not so significant. That freeness has more than a monopoly pressing down on it.
Thanks Ariba, sounds promising.
I do still hold out hope that the ECP5 FPGA will be usable in the end and that its clock distribution skew becomes manageable so hold timing analysis succeeds. I recall that the ECP5 has slightly more limited PLL capabilities compared to Altera FPGAs and the P1V's clock generator block were causing some of the drama with the P1V hold timing problems I was getting when I was trying to derive and distribute both 160MHz and 80MHz clocks from some common 480MHz PLL frequency.
I didn't have much luck with that stuff yet unfortunately but another P1V codebase may see different outcomes. I may possibly have started with a different variant of code to you (can't recall exactly as it been too long now). Might have been something from Jac's github repo instead of the original release from Chip, however I think that code has also been changing since.
Besides the other arguments, there's Intel (Altera) as a counterexample.
I don't recall any particular major corporate power ever being "the" prime mover for Linux.
Rather, what I have seen over the decades is that many such organizations have pitched in and collaborated on the Linux eco-system. Intel, IBM, Google, Facebook, Amazon and a host of others. Now even Microsoft, whose boss famously derided Linux and Open Source software as a "cancer". True. Practical necessity is the major reason why Linux and all the Free and Open Source software around has grown so well over the years.
The purchase of Altera by Intel is quite a recent development so do forgive me that oversight.
Makes me wonder whose FABS Altera devices were built in before and are they now built in Intel's FABs?
Re: Linux (Unix), It's interesting that Microsoft was such a big player in the late 70's,early 80's with it's Xenix licensing.
IIRC they licensed it to lot of companies such as Intel, IBM and even Apple.
I guess I'm a bit of an outsider. Windows, or even MS-DOS was never really a thing in my life. Except for a brief period in 1998 or so. I had spent years working on all kind of other systems. The PC and such was regarded as a toy.
The PC got serious with the arrival of the 386 in 1985. But there was not generally available 32 bit operating system till 15 years later! Linux, started in 1991 was not an attack on any duoploy, it just arrived to fill a big hole.
Meanwhile I had been working with embedded systems in various companies for many years. I noticed that often they had a hard time because some operating system or language their products depended on no longer existed. Good for me, as they hired me to help fix that mess. So at one company, when I found they were digging yet another proprietary hole for themselves, I suggested they forget thinking about the traditional embedded operating system vendors and use Linux instead. They thought I was nuts. Took a while to turn them around.
Little did I know that embedded systems builders around the world had the same idea!
I've looked at the Diamond project again. It was 94.8 MHz max and the worst path was in the ALU, so the CPU should work with that frequency. This was a 4 cog version for the 12kLUT ECP5.
I have not used the original Verilog for clock generation. I simplified it in that I used a clock input from a pin as the cpu_clock and generate a x 2 clock with a PLL for pll_clk.
I think we don't need all the configuration options of the real Propeller in a P1V, you always can modify the Verilog source for special clock settings.
Andy
One thing I noticed on the FleaFPGA Ohm board in particular is that Valentin uses a 25MHz xtal frequency, not the more common 50MHz other boards often use. That also has some impact on how the 160/80MHz can be generated - perhaps 800/10 and 800/5 are possible if the PLL multiplier and divider ranges can reach those numbers. Personally I would really like a core PLL clock of 480MHz as it lets you get 96MHz for USB use too. Though that may be still achievable in other ways if you cascade PLLs, in theory anyway.
The ECP5 used on that board has 2 PLLs. Valentin used 25MHz for getting 750MHz then divides down to 75MHz and 375MHz for the HDMI graphics clocks needed for HDTV resolutions. My thought was to also get a 50MHz clock from that first PLL (divide by 15) and feed it into the second PLL for P1V use.
Roger.
Thats pretty exciting, Andy. Is that with a -6, -7, or -8 speed grade?
BTW I looked at the warnings and the only warnings I see are the one that identifiers are used before declared - should be easy to fix.
4 Cogs use 67% of a ECP5-12, maybe 6 cogs will fit, but I need some free logic for extensions.
The ECP5-25 of the FleaOhm should easy allow 8 cogs plus extensions.
Andy
LOL, yeah same here. I think it might be the reverse of SDRAM so -6 is slower than the -8.